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Searched refs:HiethWrite (Results 1 - 4 of 4) sorted by relevance

/device/soc/hisilicon/common/platform/hieth-sf/include/internal/
H A Dmdio.h50 HiethWrite(ld, MDIO_MK_RWCTL(0, 0, 0, phyAddr, (ld)->mdioFrqdiv, regNum), MDIO_RWCTRL)
55 HiethWrite(ld, MDIO_MK_RWCTL(val, 0, 1, phyAddr, (ld)->mdioFrqdiv, regNum), MDIO_RWCTRL)
60 HiethWrite(ld, 0x00008000, MDIO_RWCTRL); \
61 HiethWrite(ld, 0x00000001, U_MDIO_PHYADDR); \
62 HiethWrite(ld, 0x00000001, D_MDIO_PHYADDR); \
63 HiethWrite(ld, 0x04631EA9, U_MDIO_ANEG_CTRL); \
64 HiethWrite(ld, 0x04631EA9, D_MDIO_ANEG_CTRL); \
65 HiethWrite(ld, 0x00000000, U_MDIO_IRQENA); \
66 HiethWrite(ld, 0x00000000, D_MDIO_IRQENA); \
H A Dhieth_pri.h122 #define HiethWrite(ld, v, ofs) \ macro
137 HiethWrite(ld, (_reg & (~_mask)) | (((unsigned long)(v) << (_shift)) & _mask), ofs); \
H A Dctrl.h276 #define HwSetRxpkgFinish(ld) HiethWrite(ld, UD_BIT_NAME(HIETH_INT_RX_RDY), GLB_RW_IRQ_RAW)
284 HiethWrite(ld, (addr), UD_REG_NAME(GLB_EQ_ADDR)); \
/device/soc/hisilicon/common/platform/hieth-sf/src/
H A Dctrl.c151 HiethWrite(ld, old | (unsigned long)irqs, GLB_RW_IRQ_ENA); in IrqEnable()
161 HiethWrite(ld, old & (~(unsigned long)irqs), GLB_RW_IRQ_ENA); in IrqDisable()
183 HiethWrite(ld, reg, GLB_HOSTMAC_H16); in HiethHwSetMacAddress()
185 HiethWrite(ld, reg, GLB_DN_HOSTMAC_H16); in HiethHwSetMacAddress()
190 HiethWrite(ld, reg, GLB_HOSTMAC_L32); in HiethHwSetMacAddress()
192 HiethWrite(ld, reg, GLB_DN_HOSTMAC_L32); in HiethHwSetMacAddress()
256 HiethWrite(ld, irqs, GLB_RW_IRQ_RAW); in HiethClearIrqstatus()
411 HiethWrite(ld, VMM_TO_DMA_ADDR((UINTPTR)NetBufGetAddress(netBuf, E_DATA_BUF)), UD_REG_NAME(GLB_IQ_ADDR)); in HiethFeedHw()

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