Home
last modified time | relevance | path

Searched refs:HI_IOCFG_REG_BASE (Results 1 - 6 of 6) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/io/
H A Dhi_flashboot_io.c41 reg_addr = HI_IOCFG_REG_BASE + IO_MUX_REG_BASE_ADDR + ((hi_u32)id << 2); /* lift shift 2 bits */ in hi_io_get_func()
53 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_get_pull()
70 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_set_driver_strength()
73 hi_reg_write((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_set_driver_strength()
85 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shift 2 bits */ in hi_io_get_driver_strength()
97 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << OFFSET_2_B)), reg_val); in hi_io_set_input_enable()
100 hi_reg_write((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << OFFSET_2_B)), reg_val); in hi_io_set_input_enable()
110 hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << OFFSET_2_B)), reg_val); in hi_io_get_input_enable()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/startup/
H A Dmain.c75 hi_reg_read(HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR, reg_val); in boot_extern_32k()
82 hi_reg_write(HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR, reg_val); in boot_extern_32k()
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H A Dhi3861_platform.h152 #define HI_IOCFG_REG_BASE 0x5000A000 macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/src/
H A Dapp_main.c113 #define iocfg_reg_addr(_x) (HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + (_x) * 4)
/device/soc/hisilicon/hi3861v100/sdk_liteos/app/wifiiot_app/src/
H A Dapp_main.c98 #define iocfg_reg_addr(_x) (HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + (_x) * 4)
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi3861_platform_base.h48 #define HI_IOCFG_REG_BASE 0x5000A000 macro

Completed in 5 milliseconds