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Searched refs:HIST_NUM (Results 1 - 10 of 10) sorted by relevance

/device/soc/hisilicon/hi3516dv300/sdk_linux/include/
H A Dhi_comm_3a.h153 HI_U32 au32HistogramMemArray[ISP_CHN_MAX_NUM][HIST_NUM];
174 HI_U32 au32HistogramMemArray[HIST_NUM];
H A Dhi_comm_isp.h2007 #define HIST_NUM 1024 macro
2037 HI_U32 au32FEHist1024Value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2047 HI_U32 au32BEHist1024Value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2059 HI_U32 au32FEHist1024Value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2066 HI_U32 au32BEHist1024Value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2628 HI_U32 au32AE_Hist1024Value[HIST_NUM]; /* R; Range:[0x0, 0xFFFFFFFF]; Format:32.0;
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/adapt/
H A Dhi_comm_3a_adapt.h89 hi_u32 histogram_mem_array[ISP_CHN_MAX_NUM][HIST_NUM];
110 hi_u32 histogram_mem_array[HIST_NUM];
H A Dhi_comm_isp_adapt.h1580 hi_u32 fe_hist1024_value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
1590 hi_u32 be_hist1024_value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
1603 hi_u32 fe_hist1024_value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
1610 hi_u32 be_hist1024_value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2059 hi_u32 ae_hist1024_value[HIST_NUM]; /* R; Range:[0x0, 0xFFFFFFFF]; Format:32.0;
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/
H A Dhi_comm_3a.h153 HI_U32 au32HistogramMemArray[ISP_CHN_MAX_NUM][HIST_NUM];
174 HI_U32 au32HistogramMemArray[HIST_NUM];
H A Dhi_comm_isp.h2008 #define HIST_NUM 1024 macro
2038 HI_U32 au32FEHist1024Value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2048 HI_U32 au32BEHist1024Value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2060 HI_U32 au32FEHist1024Value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2067 HI_U32 au32BEHist1024Value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2636 HI_U32 au32AE_Hist1024Value[HIST_NUM]; /* R; Range:[0x0, 0xFFFFFFFF]; Format:32.0;
/device/soc/hisilicon/hi3516dv300/sdk_linux/include/adapt/
H A Dhi_comm_3a_adapt.h89 hi_u32 histogram_mem_array[ISP_CHN_MAX_NUM][HIST_NUM];
110 hi_u32 histogram_mem_array[HIST_NUM];
H A Dhi_comm_isp_adapt.h1580 hi_u32 fe_hist1024_value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
1590 hi_u32 be_hist1024_value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
1603 hi_u32 fe_hist1024_value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
1610 hi_u32 be_hist1024_value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2059 hi_u32 ae_hist1024_value[HIST_NUM]; /* R; Range:[0x0, 0xFFFFFFFF]; Format:32.0;
/device/soc/hisilicon/hi3516dv300/sdk_linux/usr/sensor/include/
H A Dhi_comm_3a.h153 HI_U32 au32HistogramMemArray[ISP_CHN_MAX_NUM][HIST_NUM];
174 HI_U32 au32HistogramMemArray[HIST_NUM];
H A Dhi_comm_isp.h2007 #define HIST_NUM 1024 macro
2037 HI_U32 au32FEHist1024Value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2047 HI_U32 au32BEHist1024Value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2059 HI_U32 au32FEHist1024Value[ISP_CHN_MAX_NUM][HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2066 HI_U32 au32BEHist1024Value[HIST_NUM]; /* R; Range: [0x0, 0xFFFFFFFF]; Format:32.0;
2628 HI_U32 au32AE_Hist1024Value[HIST_NUM]; /* R; Range:[0x0, 0xFFFFFFFF]; Format:32.0;

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