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Searched refs:GPU_CONTROL_REG (Results 1 - 25 of 73) sorted by relevance

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/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_backend_gpuprops_get()
41 registers.l2_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_FEATURES)); in kbase_backend_gpuprops_get()
43 registers.core_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(CORE_FEATURES)); in kbase_backend_gpuprops_get()
47 registers.tiler_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_FEATURES)); in kbase_backend_gpuprops_get()
48 registers.mem_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MEM_FEATURES)); in kbase_backend_gpuprops_get()
49 registers.mmu_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MMU_FEATURES)); in kbase_backend_gpuprops_get()
50 registers.as_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(AS_PRESENT)); in kbase_backend_gpuprops_get()
52 registers.js_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_PRESENT)); in kbase_backend_gpuprops_get()
59 registers.js_features[i] = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_FEATURES_REG(i))); in kbase_backend_gpuprops_get()
65 registers.texture_features[i] = kbase_reg_read(kbdev, GPU_CONTROL_REG(TEXTURE_FEATURES_RE in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c36 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_gpu_time_norequest()
37 *cycle_counter = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_LO)); in kbase_backend_get_gpu_time_norequest()
38 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_gpu_time_norequest()
46 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI)); in kbase_backend_get_gpu_time_norequest()
47 *system_time = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_LO)); in kbase_backend_get_gpu_time_norequest()
48 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI)); in kbase_backend_get_gpu_time_norequest()
H A Dmali_kbase_instr_backend.c60 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_instr_hwcnt_enable_internal()
61 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | PRFCNT_SAMPLE_COMPLETED); in kbase_instr_hwcnt_enable_internal()
96 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), prfcnt_config | PRFCNT_CONFIG_MODE_OFF); in kbase_instr_hwcnt_enable_internal()
98 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), enable->dump_buffer & BASE_MEM_FLAGS_MAX); in kbase_instr_hwcnt_enable_internal()
99 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), enable->dump_buffer >> BASE_MEM_FLAGS_NR_HI_BITS); in kbase_instr_hwcnt_enable_internal()
101 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), enable->fe_bm); in kbase_instr_hwcnt_enable_internal()
103 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_EN), enable->shader_bm); in kbase_instr_hwcnt_enable_internal()
104 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_MMU_L2_EN), enable->mmu_l2_bm); in kbase_instr_hwcnt_enable_internal()
106 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN), enable->tiler_bm); in kbase_instr_hwcnt_enable_internal()
108 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFI in kbase_instr_hwcnt_enable_internal()
[all...]
H A Dmali_kbase_pm_driver.c248 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CLEAN_INV_CACHES); in mali_cci_flush_l2()
250 raw = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)); in mali_cci_flush_l2()
255 raw = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)); in mali_cci_flush_l2()
336 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg), lo); in kbase_pm_invoke()
339 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg + 4), hi); in kbase_pm_invoke()
368 lo = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg)); in kbase_pm_get_state()
369 hi = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg + 4)); in kbase_pm_get_state()
509 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_CONFIG)); in kbase_pm_l2_config_override()
524 kbase_reg_write(kbdev, GPU_CONTROL_REG(L2_CONFIG), val); in kbase_pm_l2_config_override()
1598 dev_err(kbdev->dev, "\tShader=%08x%08x\n", kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_READY_H
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c39 registers.gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_backend_gpuprops_get()
42 GPU_CONTROL_REG(L2_FEATURES)); in kbase_backend_gpuprops_get()
47 GPU_CONTROL_REG(CORE_FEATURES)); in kbase_backend_gpuprops_get()
54 kbase_reg_read(kbdev, GPU_CONTROL_REG(CORE_FEATURES)); in kbase_backend_gpuprops_get()
57 GPU_CONTROL_REG(TILER_FEATURES)); in kbase_backend_gpuprops_get()
59 GPU_CONTROL_REG(MEM_FEATURES)); in kbase_backend_gpuprops_get()
61 GPU_CONTROL_REG(MMU_FEATURES)); in kbase_backend_gpuprops_get()
63 GPU_CONTROL_REG(AS_PRESENT)); in kbase_backend_gpuprops_get()
66 GPU_CONTROL_REG(JS_PRESENT)); in kbase_backend_gpuprops_get()
74 GPU_CONTROL_REG(JS_FEATURES_RE in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_model_dummy.c87 case GPU_CONTROL_REG(SHADER_PRESENT_LO): in get_implementation_register()
89 case GPU_CONTROL_REG(TILER_PRESENT_LO): in get_implementation_register()
91 case GPU_CONTROL_REG(L2_PRESENT_LO): in get_implementation_register()
93 case GPU_CONTROL_REG(STACK_PRESENT_LO): in get_implementation_register()
96 case GPU_CONTROL_REG(SHADER_PRESENT_HI): in get_implementation_register()
97 case GPU_CONTROL_REG(TILER_PRESENT_HI): in get_implementation_register()
98 case GPU_CONTROL_REG(L2_PRESENT_HI): in get_implementation_register()
99 case GPU_CONTROL_REG(STACK_PRESENT_HI): in get_implementation_register()
1164 } else if (addr == GPU_CONTROL_REG(GPU_IRQ_MASK)) {
1173 } else if (addr == GPU_CONTROL_REG(GPU_IRQ_MAS
[all...]
H A Dmali_kbase_time.c42 GPU_CONTROL_REG(TIMESTAMP_HI)); in kbase_backend_get_gpu_time_norequest()
44 GPU_CONTROL_REG(TIMESTAMP_LO)); in kbase_backend_get_gpu_time_norequest()
46 GPU_CONTROL_REG(TIMESTAMP_HI)); in kbase_backend_get_gpu_time_norequest()
78 if ((kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)) & in timedwait_cycle_count_active()
159 GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_cycle_cnt()
161 GPU_CONTROL_REG(CYCLE_COUNT_LO)); in kbase_backend_get_cycle_cnt()
163 GPU_CONTROL_REG(CYCLE_COUNT_HI)); in kbase_backend_get_cycle_cnt()
H A Dmali_kbase_instr_backend.c63 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_instr_hwcnt_enable_internal()
64 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | in kbase_instr_hwcnt_enable_internal()
84 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), in kbase_instr_hwcnt_enable_internal()
87 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), in kbase_instr_hwcnt_enable_internal()
89 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), in kbase_instr_hwcnt_enable_internal()
92 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), in kbase_instr_hwcnt_enable_internal()
95 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_EN), in kbase_instr_hwcnt_enable_internal()
97 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_MMU_L2_EN), in kbase_instr_hwcnt_enable_internal()
100 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN), in kbase_instr_hwcnt_enable_internal()
103 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFI in kbase_instr_hwcnt_enable_internal()
[all...]
H A Dmali_kbase_pm_driver.c279 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in mali_cci_flush_l2()
283 GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)); in mali_cci_flush_l2()
290 GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)); in mali_cci_flush_l2()
374 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg), lo); in kbase_pm_invoke()
376 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg + 4), hi); in kbase_pm_invoke()
405 lo = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg)); in kbase_pm_get_state()
406 hi = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg + 4)); in kbase_pm_get_state()
547 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_CONFIG)); in kbase_pm_l2_config_override()
568 kbase_reg_write(kbdev, GPU_CONTROL_REG(ASN_HASH(i)), in kbase_pm_l2_config_override()
574 kbase_reg_write(kbdev, GPU_CONTROL_REG(L2_CONFI in kbase_pm_l2_config_override()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c35 regdump->gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID), NULL); in kbase_backend_gpuprops_get()
38 GPU_CONTROL_REG(L2_FEATURES), NULL); in kbase_backend_gpuprops_get()
40 GPU_CONTROL_REG(SUSPEND_SIZE), NULL); in kbase_backend_gpuprops_get()
42 GPU_CONTROL_REG(TILER_FEATURES), NULL); in kbase_backend_gpuprops_get()
44 GPU_CONTROL_REG(MEM_FEATURES), NULL); in kbase_backend_gpuprops_get()
46 GPU_CONTROL_REG(MMU_FEATURES), NULL); in kbase_backend_gpuprops_get()
48 GPU_CONTROL_REG(AS_PRESENT), NULL); in kbase_backend_gpuprops_get()
50 GPU_CONTROL_REG(JS_PRESENT), NULL); in kbase_backend_gpuprops_get()
54 GPU_CONTROL_REG(JS_FEATURES_REG(i)), NULL); in kbase_backend_gpuprops_get()
58 GPU_CONTROL_REG(TEXTURE_FEATURES_RE in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c33 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), in kbase_backend_get_gpu_time()
36 GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL); in kbase_backend_get_gpu_time()
37 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), in kbase_backend_get_gpu_time()
45 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), in kbase_backend_get_gpu_time()
48 GPU_CONTROL_REG(TIMESTAMP_LO), NULL); in kbase_backend_get_gpu_time()
49 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), in kbase_backend_get_gpu_time()
88 GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL); in kbase_wait_write_flush()
H A Dmali_kbase_instr_backend.c49 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbasep_instr_hwcnt_cacheclean()
50 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbasep_instr_hwcnt_cacheclean()
57 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), in kbasep_instr_hwcnt_cacheclean()
100 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_instr_hwcnt_enable_internal()
101 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | in kbase_instr_hwcnt_enable_internal()
144 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), in kbase_instr_hwcnt_enable_internal()
147 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), in kbase_instr_hwcnt_enable_internal()
149 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), in kbase_instr_hwcnt_enable_internal()
151 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), in kbase_instr_hwcnt_enable_internal()
153 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_E in kbase_instr_hwcnt_enable_internal()
[all...]
H A Dmali_kbase_pm_driver.c155 GPU_CONTROL_REG(GPU_COMMAND), in mali_cci_flush_l2()
160 GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), in mali_cci_flush_l2()
167 GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), in mali_cci_flush_l2()
278 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg), lo, NULL); in kbase_pm_invoke()
281 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg + 4), hi, NULL); in kbase_pm_invoke()
309 lo = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg), NULL); in kbase_pm_get_state()
310 hi = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg + 4), NULL); in kbase_pm_get_state()
958 GPU_CONTROL_REG(SHADER_READY_HI), NULL), in kbase_pm_check_transitions_sync()
960 GPU_CONTROL_REG(SHADER_READY_LO), in kbase_pm_check_transitions_sync()
964 GPU_CONTROL_REG(TILER_READY_H in kbase_pm_check_transitions_sync()
[all...]
H A Dmali_kbase_device_hw.c214 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS), NULL); in kbase_report_gpu_fault()
216 GPU_CONTROL_REG(GPU_FAULTADDRESS_HI), NULL) << 32; in kbase_report_gpu_fault()
218 GPU_CONTROL_REG(GPU_FAULTADDRESS_LO), NULL); in kbase_report_gpu_fault()
244 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val, NULL); in kbase_gpu_interrupt()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_gpuprops_backend.c30 regdump->gpu_id = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID), NULL); in kbase_backend_gpuprops_get()
32 regdump->l2_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_FEATURES), NULL); in kbase_backend_gpuprops_get()
33 regdump->suspend_size = kbase_reg_read(kbdev, GPU_CONTROL_REG(SUSPEND_SIZE), NULL); in kbase_backend_gpuprops_get()
34 regdump->tiler_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_FEATURES), NULL); in kbase_backend_gpuprops_get()
35 regdump->mem_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MEM_FEATURES), NULL); in kbase_backend_gpuprops_get()
36 regdump->mmu_features = kbase_reg_read(kbdev, GPU_CONTROL_REG(MMU_FEATURES), NULL); in kbase_backend_gpuprops_get()
37 regdump->as_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(AS_PRESENT), NULL); in kbase_backend_gpuprops_get()
38 regdump->js_present = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_PRESENT), NULL); in kbase_backend_gpuprops_get()
41 regdump->js_features[i] = kbase_reg_read(kbdev, GPU_CONTROL_REG(JS_FEATURES_REG(i)), NULL); in kbase_backend_gpuprops_get()
45 regdump->texture_features[i] = kbase_reg_read(kbdev, GPU_CONTROL_REG(TEXTURE_FEATURES_RE in kbase_backend_gpuprops_get()
[all...]
H A Dmali_kbase_time.c33 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), NULL); in kbase_backend_get_gpu_time()
34 *cycle_counter = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL); in kbase_backend_get_gpu_time()
35 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(CYCLE_COUNT_HI), NULL); in kbase_backend_get_gpu_time()
42 hi1 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), NULL); in kbase_backend_get_gpu_time()
43 *system_time = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_LO), NULL); in kbase_backend_get_gpu_time()
44 hi2 = kbase_reg_read(kbdev, GPU_CONTROL_REG(TIMESTAMP_HI), NULL); in kbase_backend_get_gpu_time()
81 new_count = kbase_reg_read(kctx->kbdev, GPU_CONTROL_REG(CYCLE_COUNT_LO), NULL); in kbase_wait_write_flush()
H A Dmali_kbase_instr_backend.c44 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbasep_instr_hwcnt_cacheclean()
45 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | CLEAN_CACHES_COMPLETED, NULL); in kbasep_instr_hwcnt_cacheclean()
51 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CLEAN_INV_CACHES, NULL); in kbasep_instr_hwcnt_cacheclean()
92 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), NULL); in kbase_instr_hwcnt_enable_internal()
93 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | PRFCNT_SAMPLE_COMPLETED, NULL); in kbase_instr_hwcnt_enable_internal()
131 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), prfcnt_config | PRFCNT_CONFIG_MODE_OFF, kctx); in kbase_instr_hwcnt_enable_internal()
133 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO), setup->dump_buffer & 0xFFFFFFFF, kctx); in kbase_instr_hwcnt_enable_internal()
134 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI), setup->dump_buffer >> 0x20, kctx); in kbase_instr_hwcnt_enable_internal()
135 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN), setup->jm_bm, kctx); in kbase_instr_hwcnt_enable_internal()
136 kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_E in kbase_instr_hwcnt_enable_internal()
[all...]
H A Dmali_kbase_pm_driver.c147 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CLEAN_INV_CACHES, NULL); in mali_cci_flush_l2()
149 raw = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), NULL); in mali_cci_flush_l2()
154 raw = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), NULL); in mali_cci_flush_l2()
257 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg), lo, NULL); in kbase_pm_invoke()
261 kbase_reg_write(kbdev, GPU_CONTROL_REG(reg + 4), hi, NULL); in kbase_pm_invoke()
289 lo = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg), NULL); in kbase_pm_get_state()
290 hi = kbase_reg_read(kbdev, GPU_CONTROL_REG(reg + 4), NULL); in kbase_pm_get_state()
871 dev_err(kbdev->dev, "\tShader=%08x%08x\n", kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_READY_HI), NULL), in kbase_pm_check_transitions_sync()
872 kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_READY_LO), NULL)); in kbase_pm_check_transitions_sync()
873 dev_err(kbdev->dev, "\tTiler =%08x%08x\n", kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_READY_H in kbase_pm_check_transitions_sync()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/
H A Dmali_kbase_device_hw.c35 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_is_gpu_removed()
51 !(kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)) & in busy_wait_cache_clean_irq()
66 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), in busy_wait_cache_clean_irq()
92 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_cache_flush_and_busy_wait()
95 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_cache_flush_and_busy_wait()
111 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), in kbase_gpu_cache_flush_and_busy_wait()
117 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), flush_op); in kbase_gpu_cache_flush_and_busy_wait()
150 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_start_cache_clean_nolock()
151 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_start_cache_clean_nolock()
155 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAN in kbase_gpu_start_cache_clean_nolock()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/
H A Dmali_kbase_device_hw.c75 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_ID)); in kbase_is_gpu_removed()
98 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_gpu_start_cache_clean_nolock()
99 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask | CLEAN_CACHES_COMPLETED); in kbase_gpu_start_cache_clean_nolock()
102 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CLEAN_INV_CACHES); in kbase_gpu_start_cache_clean_nolock()
136 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND), GPU_COMMAND_CLEAN_INV_CACHES); in kbase_clean_caches_done()
139 irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)); in kbase_clean_caches_done()
140 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask & ~CLEAN_CACHES_COMPLETED); in kbase_clean_caches_done()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_jm.c43 u32 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS)); in kbase_report_gpu_fault()
44 u64 address = (u64)kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTADDRESS_HI)) << 32; in kbase_report_gpu_fault()
46 address |= kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTADDRESS_LO)); in kbase_report_gpu_fault()
71 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val); in kbase_gpu_interrupt()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/device/backend/
H A Dmali_kbase_device_hw_jm.c41 u32 status = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS)); in kbase_report_gpu_fault()
43 GPU_CONTROL_REG(GPU_FAULTADDRESS_HI)) << 32; in kbase_report_gpu_fault()
46 GPU_CONTROL_REG(GPU_FAULTADDRESS_LO)); in kbase_report_gpu_fault()
70 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val); in kbase_gpu_interrupt()
H A Dmali_kbase_device_hw_csf.c45 GPU_CONTROL_REG(GPU_FAULTADDRESS_HI)) << 32; in kbase_report_gpu_fault()
48 GPU_CONTROL_REG(GPU_FAULTADDRESS_LO)); in kbase_report_gpu_fault()
59 GPU_CONTROL_REG(GPU_FAULTSTATUS)); in kbase_gpu_fault_interrupt()
102 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), in kbase_gpu_interrupt()
137 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val); in kbase_gpu_interrupt()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_reset_gpu.c240 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT)), in kbase_csf_debug_dump_registers()
241 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_STATUS)), in kbase_csf_debug_dump_registers()
242 kbase_reg_read(kbdev, GPU_CONTROL_REG(MCU_STATUS))); in kbase_csf_debug_dump_registers()
246 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_FAULTSTATUS))); in kbase_csf_debug_dump_registers()
248 kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK)), in kbase_csf_debug_dump_registers()
252 kbase_reg_read(kbdev, GPU_CONTROL_REG(PWR_OVERRIDE0)), in kbase_csf_debug_dump_registers()
253 kbase_reg_read(kbdev, GPU_CONTROL_REG(PWR_OVERRIDE1))); in kbase_csf_debug_dump_registers()
255 kbase_reg_read(kbdev, GPU_CONTROL_REG(SHADER_CONFIG)), in kbase_csf_debug_dump_registers()
256 kbase_reg_read(kbdev, GPU_CONTROL_REG(L2_MMU_CONFIG)), in kbase_csf_debug_dump_registers()
257 kbase_reg_read(kbdev, GPU_CONTROL_REG(TILER_CONFI in kbase_csf_debug_dump_registers()
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/tests/mali_kutf_irq_test/
H A Dmali_kutf_irq_test_main.c88 val = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_STATUS), NULL); in kbase_gpu_irq_custom_handler()
95 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val, in kbase_gpu_irq_custom_handler()
191 kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_RAWSTAT), in mali_kutf_irq_latency()

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