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Help
Searched
refs:GLB_CTL_BASE
(Results
1 - 3
of
3
) sorted by relevance
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H
A
D
hi3861_platform_base.h
138
#define
GLB_CTL_BASE
0x50000000
macro
139
#define GLB_CTL_SYS_CTL_ID_REG (
GLB_CTL_BASE
+ 0x0)
140
#define GLB_CTL_GP_REG0_REG (
GLB_CTL_BASE
+ 0x10)
141
#define GLB_CTL_GP_REG1_REG (
GLB_CTL_BASE
+ 0x14)
142
#define GLB_CTL_GP_REG2_REG (
GLB_CTL_BASE
+ 0x18)
143
#define GLB_CTL_GP_REG3_REG (
GLB_CTL_BASE
+ 0x1C)
144
#define GLB_CTL_AON_SOFT_RST_W_REG (
GLB_CTL_BASE
+ 0x20)
145
#define GLB_CTL_SOFT_RST_WCPU_REG (
GLB_CTL_BASE
+ 0x24)
146
#define GLB_CTL_SOFT_GLB_RST_REG (
GLB_CTL_BASE
+ 0x28)
147
#define GLB_CTL_GLB_WDT_RST_SEL_REG (
GLB_CTL_BASE
[all...]
/device/soc/hisilicon/hi3861v100/sdk_liteos/boot/commonboot/
H
A
D
hi3861_platform.h
38
#define
GLB_CTL_BASE
0x50000000
macro
39
#define GLB_CTL_SYS_CTL_ID_REG (
GLB_CTL_BASE
+ 0x0)
40
#define GLB_CTL_AON_SOFT_RST_W_REG (
GLB_CTL_BASE
+ 0x20)
41
#define GLB_CTL_SOFT_RST_WCPU_REG (
GLB_CTL_BASE
+ 0x24)
42
#define GLB_CTL_SOFT_GLB_RESET_CFG (
GLB_CTL_BASE
+ 0x28)
43
#define GLB_CTL_GLB_WDT_RST_SEL_REG (
GLB_CTL_BASE
+ 0x30)
44
#define GLB_CTL_WDT_RST_SEL_REG (
GLB_CTL_BASE
+ 0x34)
45
#define GLB_CTL_AON_CKEN_REG (
GLB_CTL_BASE
+ 0x40)
46
#define GLB_CTL_GLB_AON_32K_CLKEN_REG (
GLB_CTL_BASE
+ 0x50)
47
#define GLB_CTL_A32K_DIV_REG (
GLB_CTL_BASE
[all...]
H
A
D
boot_rom.h
24
#define GLB_CTL_GP_REG0_REG (
GLB_CTL_BASE
+ 0x10)
25
#define GLB_CTL_GP_REG1_REG (
GLB_CTL_BASE
+ 0x14)
26
#define GLB_CTL_GP_REG2_REG (
GLB_CTL_BASE
+ 0x18)
27
#define GLB_CTL_GP_REG3_REG (
GLB_CTL_BASE
+ 0x1C)
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