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Searched refs:DIAG_CTL_CLOCK_TEST_DIV (Results 1 - 2 of 2) sorted by relevance

/device/soc/hisilicon/hi3861v100/sdk_liteos/app/demo/init/
H A Dapp_io_init.c24 hi_reg_write16(DIAG_CTL_CLOCK_TEST_DIV, 0x0); in app_io_set_gpio2_clkout_enable()
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi3861_platform_base.h432 #define DIAG_CTL_CLOCK_TEST_DIV (DIAG_CTL_BASE + 0x0D4) /* clock test div */ macro

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