CLK_PCIEPHY0_DIV (reference) in projects: device - OpenGrok search results

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Searched refs:CLK_PCIEPHY0_DIV (Results 1 - 3 of 3) sorted by relevance

/device/soc/rockchip/common/sdk_linux/include/dt-bindings/clock/
H A D	rk3568-cru.h	`42 #define CLK_PCIEPHY0_DIV 29 macro`
/device/soc/rockchip/rk3588/kernel/include/dt-bindings/clock/
H A D	rk3568-cru.h	`42 #define CLK_PCIEPHY0_DIV 29 macro`
/device/soc/rockchip/rk3566/vendor/drivers/clk/
H A D	clk-rk3568.c	`1097 COMPOSITE_NOMUX(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "ppll_ph0", 0, RK3568_PMU_CLKSEL_CON(9), 0, 3, DFLAGS,`

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