CACHE_LINE_SIZE (reference) in projects: device - OpenGrok search results

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Searched refs:CACHE_LINE_SIZE (Results 1 - 6 of 6) sorted by relevance

/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/linux/mmz/
H A D	mmz_userdev.c	`544 end_vir_addr = (unsigned int)(uintptr_t)vir_addr + size - CACHE_LINE_SIZE; 551 end_phy_addr = phy_addr + size - CACHE_LINE_SIZE; 834 area.dirty_phys_start &= ~(CACHE_LINE_SIZE - 1); 836 virt_addr &= ~(CACHE_LINE_SIZE - 1); 839 (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);`
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/targets/hi3861v100/include/
H A D	target_config.h	`232 #define CACHE_LINE_SIZE 32 // cache line size, macro`
/device/soc/rockchip/rk2206/hardware/lib/CMSIS/Device/RK2206/Include/
H A D	soc.h	`200 #define CACHE_LINE_SIZE (0x1U << CACHE_LINE_SHIFT) macro`
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/osal/include/
H A D	osal_mmz.h	`24 #define CACHE_LINE_SIZE 0x40 macro`
/device/soc/hisilicon/hi3516dv300/sdk_linux/include/
H A D	osal_mmz.h	`21 #define CACHE_LINE_SIZE 0x40 macro`
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/
H A D	osal_mmz.h	`22 #define CACHE_LINE_SIZE 0x40 macro`

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