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Searched refs:CACHE_ALIGNED_SIZE (Results 1 - 14 of 14) sorted by relevance

/device/qemu/arm_virt/liteos_a_mini/board/
H A Dtarget_config.h32 #define CACHE_ALIGNED_SIZE 64 macro
/device/board/hisilicon/hispark_aries/liteos_a/board/
H A Dtarget_config.h31 #define CACHE_ALIGNED_SIZE 64 macro
/device/qemu/arm_virt/liteos_a/board/
H A Dtarget_config.h32 #define CACHE_ALIGNED_SIZE 64 macro
/device/board/hisilicon/hispark_taurus/liteos_a/board/
H A Dtarget_config.h36 #define CACHE_ALIGNED_SIZE 64 macro
/device/soc/hisilicon/common/platform/hieth-sf/src/
H A Dinterface.c132 uint32_t start = (uintptr_t)addr & ~(CACHE_ALIGNED_SIZE - 1); in NetDmaCacheInv()
135 end = ALIGN(end, CACHE_ALIGNED_SIZE); in NetDmaCacheInv()
141 uint32_t start = (uintptr_t)addr & ~(CACHE_ALIGNED_SIZE - 1); in NetDmaCacheClean()
144 end = ALIGN(end, CACHE_ALIGNED_SIZE); in NetDmaCacheClean()
H A Dctrl.c393 netBuf = NetBufAlloc(ALIGN(HIETH_MAX_FRAME_SIZE + ETH_PAD_SIZE + CACHE_ALIGNED_SIZE, CACHE_ALIGNED_SIZE)); in HiethFeedHw()
401 CACHE_ALIGNED_SIZE) - (uintptr_t)NetBufGetAddress(netBuf, E_DATA_BUF)); in HiethFeedHw()
/device/soc/hisilicon/common/platform/mmc/sdhci/
H A Dsdhci.c79 uint32_t start = (uintptr_t)addr & ~(CACHE_ALIGNED_SIZE - 1); in SdhciDmaCacheClean()
82 end = ALIGN(end, CACHE_ALIGNED_SIZE); in SdhciDmaCacheClean()
89 uint32_t start = (uintptr_t)addr & ~(CACHE_ALIGNED_SIZE - 1); in SdhciDmaCacheInv()
92 end = ALIGN(end, CACHE_ALIGNED_SIZE); in SdhciDmaCacheInv()
319 (void)memset_s(admaDesc, ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE), in SdhciAdmaTablePre()
320 0, ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE)); in SdhciAdmaTablePre()
358 ALIGN(host->admaDescSize, CACHE_ALIGNED_SIZE)); in SdhciAdmaTablePre()
485 host->alignedBuff = (uint8_t *)OsalMemAllocAlign(CACHE_ALIGNED_SIZE, ALIGN(len, CACHE_ALIGNED_SIZE)); in SdhciFillDmaSg()
1710 host->admaDesc = (void *)OsalMemAllocAlign(CACHE_ALIGNED_SIZE, ALIG in SdhciFillAdmaInfo()
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/device/board/hisilicon/hispark_aries/liteos_a/board/include/asm/
H A Dplatform.h120 #define CACHE_ALIGNED_SIZE 64 macro
/device/soc/hisilicon/common/platform/mmc/himci_v200/
H A Dhimci.c274 uint32_t start = (uintptr_t)addr & ~(CACHE_ALIGNED_SIZE - 1); in HimciDmaCacheClean()
277 end = ALIGN(end, CACHE_ALIGNED_SIZE); in HimciDmaCacheClean()
284 uint32_t start = (uintptr_t)addr & ~(CACHE_ALIGNED_SIZE - 1); in HimciDmaCacheInv()
287 end = ALIGN(end, CACHE_ALIGNED_SIZE); in HimciDmaCacheInv()
636 host->alignedBuff = (uint8_t *)OsalMemAllocAlign(CACHE_ALIGNED_SIZE, ALIGN(len, CACHE_ALIGNED_SIZE)); in HimciFillDmaSg()
698 if ((sgPhyAddr & (CACHE_ALIGNED_SIZE - 1)) != 0) { in HimciSetupData()
1773 host->dmaVaddr = (uint32_t *)LOS_DmaMemAlloc(&host->dmaPaddr, HIMCI_PAGE_SIZE, CACHE_ALIGNED_SIZE, DMA_CACHE); in HimciHostInit()
/device/board/hisilicon/hispark_taurus/liteos_a/board/include/asm/
H A Dplatform.h143 #define CACHE_ALIGNED_SIZE 64 macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/include/
H A Dhi_types_base.h294 #ifndef CACHE_ALIGNED_SIZE
295 #define CACHE_ALIGNED_SIZE 32 macro
H A Dhi3861_platform_base.h135 #define CACHE_ALIGNED_SIZE 32 macro
/device/soc/hisilicon/common/platform/mtd/hifmc100/common/
H A Dhifmc100.h48 #define HIFMC_DMA_ALIGN_SIZE (CACHE_ALIGNED_SIZE)
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/oal/
H A Doal_sdio_host.c2167 hi_sdio->sdio_align_buff = memalign(CACHE_ALIGNED_SIZE, SKB_DATA_ALIGN(HISDIO_BLOCK_SIZE)); in oal_sdio_init_module()
2181 hi_sdio->scatt_buff.buff = memalign(CACHE_ALIGNED_SIZE, tx_scatt_buff_len); in oal_sdio_init_module()

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