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Searched refs:BASE_MAX_NR_CLOCKS_REGULATORS (Results 1 - 15 of 15) sorted by relevance

/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_clk_rate_trace_mgr.c74 if (WARN_ON(!callbacks) || WARN_ON(!gpu_clk_handle) || WARN_ON(index >= BASE_MAX_NR_CLOCKS_REGULATORS)) { in gpu_clk_data_init()
129 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_init()
174 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_term()
199 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_gpu_active()
229 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_gpu_idle()
H A Dmali_kbase_devfreq.c111 unsigned long freqs[BASE_MAX_NR_CLOCKS_REGULATORS] = {0}; in kbase_devfreq_target()
112 unsigned long old_freqs[BASE_MAX_NR_CLOCKS_REGULATORS] = {0}; in kbase_devfreq_target()
113 unsigned long volts[BASE_MAX_NR_CLOCKS_REGULATORS] = {0}; in kbase_devfreq_target()
428 u64 core_mask, opp_freq, real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbase_devfreq_init_core_mask_table()
431 u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbase_devfreq_init_core_mask_table()
445 #if BASE_MAX_NR_CLOCKS_REGULATORS > 1 in kbase_devfreq_init_core_mask_table()
H A Dmali_kbase_pm_metrics.c80 memset(kbdev->pm.backend.metrics.active_cl_ctx, 0, sizeof(u32) * BASE_MAX_NR_CLOCKS_REGULATORS); in kbasep_pm_metrics_init()
256 memset(kbdev->pm.backend.metrics.active_cl_ctx, 0, sizeof(u32) * BASE_MAX_NR_CLOCKS_REGULATORS); in kbase_pm_metrics_active_calc()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_defs.h143 #define BASE_MAX_NR_CLOCKS_REGULATORS (2) macro
145 #define BASE_MAX_NR_CLOCKS_REGULATORS (1) macro
342 struct kbase_clk_data *clks[BASE_MAX_NR_CLOCKS_REGULATORS];
514 u64 real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];
515 u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS];
890 struct clk *clocks[BASE_MAX_NR_CLOCKS_REGULATORS];
893 struct regulator *regulators[BASE_MAX_NR_CLOCKS_REGULATORS];
975 unsigned long current_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];
977 unsigned long current_voltages[BASE_MAX_NR_CLOCKS_REGULATORS];
H A Dmali_kbase_hwcnt_backend_jm.c91 u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];
92 u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];
H A Dmali_kbase_core_linux.c4110 BUILD_BUG_ON(ARRAY_SIZE(regulator_names) < BASE_MAX_NR_CLOCKS_REGULATORS); in power_control_init()
4127 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_init()
4137 while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) { in power_control_init()
4157 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_init()
4174 while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) { in power_control_init()
4189 kbdev->dev, regulator_names, BASE_MAX_NR_CLOCKS_REGULATORS); in power_control_init()
4208 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_init()
4238 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_term()
4250 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_term()
H A Dmali_kbase_hwcnt_gpu.c173 for (clk = 0; clk < BASE_MAX_NR_CLOCKS_REGULATORS; clk++) { in kbase_hwcnt_gpu_info_init()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_clk_rate_trace_mgr.c157 WARN_ON(index >= BASE_MAX_NR_CLOCKS_REGULATORS)) in gpu_clk_data_init()
219 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_init()
264 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_term()
289 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_gpu_active()
317 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_gpu_idle()
H A Dmali_kbase_devfreq.c457 real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbase_devfreq_init_core_mask_table()
460 u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbase_devfreq_init_core_mask_table()
475 #if BASE_MAX_NR_CLOCKS_REGULATORS > 1 in kbase_devfreq_init_core_mask_table()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_defs.h155 #define BASE_MAX_NR_CLOCKS_REGULATORS (4) macro
364 struct kbase_clk_data *clks[BASE_MAX_NR_CLOCKS_REGULATORS];
533 u64 real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];
534 u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS];
975 struct clk *clocks[BASE_MAX_NR_CLOCKS_REGULATORS];
979 struct regulator *regulators[BASE_MAX_NR_CLOCKS_REGULATORS];
1068 unsigned long current_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];
1070 unsigned long current_voltages[BASE_MAX_NR_CLOCKS_REGULATORS];
H A Dmali_kbase_hwcnt_backend_csf.c35 #ifndef BASE_MAX_NR_CLOCKS_REGULATORS
36 #define BASE_MAX_NR_CLOCKS_REGULATORS 4 macro
249 u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];
250 u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];
279 u64 cycle_counts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbasep_hwcnt_backend_csf_cc_initial_sample()
298 u64 cycle_counts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbasep_hwcnt_backend_csf_cc_update()
1956 if (csf_info->prfcnt_info.clk_cnt > BASE_MAX_NR_CLOCKS_REGULATORS) in kbase_hwcnt_backend_csf_metadata_init()
H A Dmali_kbase_hwcnt_backend_jm.c122 u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];
123 u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];
165 for (clk = 0; clk < BASE_MAX_NR_CLOCKS_REGULATORS; clk++) { in kbasep_hwcnt_backend_jm_gpu_info_init()
H A Dmali_kbase_core_linux.c4449 while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) in power_control_init()
4468 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_init()
4486 while ((i > 0) && (i < BASE_MAX_NR_CLOCKS_REGULATORS)) { in power_control_init()
4536 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) in power_control_init()
4558 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_term()
4568 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_term()
H A Dmali_kbase_hwcnt_backend_csf_if_fw.c769 for (clk = 0; clk < BASE_MAX_NR_CLOCKS_REGULATORS; clk++) { in kbasep_hwcnt_backend_csf_if_fw_ctx_create()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/tests/mali_kutf_clk_rate_trace/kernel/
H A Dmali_kutf_clk_rate_trace_test.c96 struct clk_trace_snapshot snapshot[BASE_MAX_NR_CLOCKS_REGULATORS];
833 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in mali_kutf_clk_rate_trace_create_fixture()

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