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Searched refs:BASE_JM_MAX_NR_SLOTS (Results 1 - 25 of 32) sorted by relevance

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/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/
H A Dmali_kbase_js_defs.h184 u64 slot_affinities[BASE_JM_MAX_NR_SLOTS];
192 s8 slot_affinity_refcount[BASE_JM_MAX_NR_SLOTS][64];
222 struct list_head ctx_list_pullable[BASE_JM_MAX_NR_SLOTS];
227 struct list_head ctx_list_unpullable[BASE_JM_MAX_NR_SLOTS];
236 base_jd_core_req js_reqs[BASE_JM_MAX_NR_SLOTS];
313 struct list_head ctx_list_entry[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_defs.h128 #define BASE_JM_MAX_NR_SLOTS 3 macro
816 u8 slot_atoms_submitted[BASE_JM_MAX_NR_SLOTS];
861 u64 debug_core_mask[BASE_JM_MAX_NR_SLOTS];
936 s8 slot_submit_count_irq[BASE_JM_MAX_NR_SLOTS];
1431 struct jsctx_queue jsctx_queue[KBASE_JS_ATOM_SCHED_PRIO_COUNT][BASE_JM_MAX_NR_SLOTS];
1436 atomic_t atoms_pulled_slot[BASE_JM_MAX_NR_SLOTS];
1439 int atoms_pulled_slot_pri[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
1443 bool blocked_js[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
H A Dmali_kbase_js.h685 KBASE_DEBUG_ASSERT(js >= 0 && js <= BASE_JM_MAX_NR_SLOTS); in kbasep_js_set_job_retry_submit_slot()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/jm/
H A Dmali_kbase_js_defs.h298 u64 slot_affinities[BASE_JM_MAX_NR_SLOTS];
299 s8 slot_affinity_refcount[BASE_JM_MAX_NR_SLOTS][64];
302 struct list_head ctx_list_pullable[BASE_JM_MAX_NR_SLOTS]
304 struct list_head ctx_list_unpullable[BASE_JM_MAX_NR_SLOTS]
308 base_jd_core_req js_reqs[BASE_JM_MAX_NR_SLOTS];
376 struct list_head ctx_list_entry[BASE_JM_MAX_NR_SLOTS];
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/
H A Dmali_kbase_js_defs.h189 u64 slot_affinities[BASE_JM_MAX_NR_SLOTS];
197 s8 slot_affinity_refcount[BASE_JM_MAX_NR_SLOTS][64];
227 struct list_head ctx_list_pullable[BASE_JM_MAX_NR_SLOTS];
232 struct list_head ctx_list_unpullable[BASE_JM_MAX_NR_SLOTS];
241 base_jd_core_req js_reqs[BASE_JM_MAX_NR_SLOTS];
319 struct list_head ctx_list_entry[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_defs.h133 #define BASE_JM_MAX_NR_SLOTS 3 macro
825 u8 slot_atoms_submitted[BASE_JM_MAX_NR_SLOTS];
871 u64 debug_core_mask[BASE_JM_MAX_NR_SLOTS];
946 s8 slot_submit_count_irq[BASE_JM_MAX_NR_SLOTS];
1450 [KBASE_JS_ATOM_SCHED_PRIO_COUNT][BASE_JM_MAX_NR_SLOTS];
1455 atomic_t atoms_pulled_slot[BASE_JM_MAX_NR_SLOTS];
1458 int atoms_pulled_slot_pri[BASE_JM_MAX_NR_SLOTS][
1463 bool blocked_js[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
H A Dmali_kbase_js.h692 KBASE_DEBUG_ASSERT(0 <= js && js <= BASE_JM_MAX_NR_SLOTS); in kbasep_js_set_job_retry_submit_slot()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/jm/
H A Dmali_kbase_js_defs.h228 u64 slot_affinities[BASE_JM_MAX_NR_SLOTS];
236 s8 slot_affinity_refcount[BASE_JM_MAX_NR_SLOTS][64];
248 struct list_head ctx_list_pullable[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
253 struct list_head ctx_list_unpullable[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
262 base_jd_core_req js_reqs[BASE_JM_MAX_NR_SLOTS];
357 struct list_head ctx_list_entry[BASE_JM_MAX_NR_SLOTS];
/device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_js_affinity.c201 u64 new_affinities[BASE_JM_MAX_NR_SLOTS]; in kbase_js_affinity_would_violate()
204 KBASE_DEBUG_ASSERT(js < BASE_JM_MAX_NR_SLOTS); in kbase_js_affinity_would_violate()
220 KBASE_DEBUG_ASSERT(js < BASE_JM_MAX_NR_SLOTS); in kbase_js_affinity_retain_slot_cores()
247 KBASE_DEBUG_ASSERT(js < BASE_JM_MAX_NR_SLOTS); in kbase_js_affinity_release_slot_cores()
H A Dmali_kbase_jm_defs.h76 struct slot_rb slot_rb[BASE_JM_MAX_NR_SLOTS];
/device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_js_affinity.c217 u64 new_affinities[BASE_JM_MAX_NR_SLOTS]; in kbase_js_affinity_would_violate()
220 KBASE_DEBUG_ASSERT(js < BASE_JM_MAX_NR_SLOTS); in kbase_js_affinity_would_violate()
238 KBASE_DEBUG_ASSERT(js < BASE_JM_MAX_NR_SLOTS); in kbase_js_affinity_retain_slot_cores()
267 KBASE_DEBUG_ASSERT(js < BASE_JM_MAX_NR_SLOTS); in kbase_js_affinity_release_slot_cores()
H A Dmali_kbase_jm_defs.h79 struct slot_rb slot_rb[BASE_JM_MAX_NR_SLOTS];
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/
H A Dmali_kbase_defs.h91 #define BASE_JM_MAX_NR_SLOTS 3 macro
383 u64 debug_core_mask[BASE_JM_MAX_NR_SLOTS];
1574 struct jsctx_queue jsctx_queue[KBASE_JS_ATOM_SCHED_PRIO_COUNT][BASE_JM_MAX_NR_SLOTS];
1581 atomic_t atoms_pulled_slot[BASE_JM_MAX_NR_SLOTS];
1582 int atoms_pulled_slot_pri[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
1584 bool blocked_js[BASE_JM_MAX_NR_SLOTS][KBASE_JS_ATOM_SCHED_PRIO_COUNT];
H A Dmali_kbase_hwaccess_defs.h45 struct kbase_context *active_kctx[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_jm.c119 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) { in kbase_jm_idle_ctx()
H A Dmali_kbase_js.c537 for (i = 0; i < BASE_JM_MAX_NR_SLOTS; ++i) { in kbasep_js_kctx_init()
560 for (j = 0; j < BASE_JM_MAX_NR_SLOTS; j++) { in kbasep_js_kctx_init()
2105 if ((katom->core_req & BASE_JD_REQ_JOB_SLOT) && (katom->jobslot >= BASE_JM_MAX_NR_SLOTS)) {
3127 struct kbase_context *last_active[BASE_JM_MAX_NR_SLOTS];
3129 bool ctx_waiting[BASE_JM_MAX_NR_SLOTS];
3139 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) {
3271 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) {
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_pm_metrics.c79 memset(kbdev->pm.backend.metrics.active_gl_ctx, 0, sizeof(u32) * BASE_JM_MAX_NR_SLOTS); in kbasep_pm_metrics_init()
144 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) { in kbase_pm_get_dvfs_utilisation_calc()
255 memset(kbdev->pm.backend.metrics.active_gl_ctx, 0, sizeof(u32) * BASE_JM_MAX_NR_SLOTS); in kbase_pm_metrics_active_calc()
259 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) { in kbase_pm_metrics_active_calc()
H A Dmali_kbase_jm_defs.h80 struct slot_rb slot_rb[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_jm_as.c208 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) { in kbase_backend_use_ctx()
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/
H A Dmali_kbase_hwaccess_defs.h44 struct kbase_context *active_kctx[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_defs.h86 #define BASE_JM_MAX_NR_SLOTS 3 macro
424 u64 debug_core_mask[BASE_JM_MAX_NR_SLOTS];
1753 [KBASE_JS_ATOM_SCHED_PRIO_COUNT][BASE_JM_MAX_NR_SLOTS];
1754 struct kbase_jsctx_slot_tracking slot_tracking[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_jm.c118 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) { in kbase_jm_idle_ctx()
H A Dmali_kbase_js.c650 for (i = 0; i < BASE_JM_MAX_NR_SLOTS; ++i) in kbasep_js_kctx_init()
675 for (j = 0; j < BASE_JM_MAX_NR_SLOTS; j++) { in kbasep_js_kctx_init()
2494 (katom->jobslot >= BASE_JM_MAX_NR_SLOTS))
3605 struct kbase_context *last_active[BASE_JM_MAX_NR_SLOTS];
3607 bool ctx_waiting[BASE_JM_MAX_NR_SLOTS];
3620 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) {
3802 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) {
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_jm_defs.h101 struct slot_rb slot_rb[BASE_JM_MAX_NR_SLOTS];
H A Dmali_kbase_jm_as.c220 for (js = 0; js < BASE_JM_MAX_NR_SLOTS; js++) { in kbase_backend_use_ctx()

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