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Searched refs:regSize (Results 1 - 18 of 18) sorted by relevance

/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/
H A Dx64_proepilog.cpp44 uint32 regSize = regByteSize * kBitsPerByte; in GenerateCalleeSavedRegs() local
45 DEBUG_ASSERT((regSize == k32BitSize || regSize == k64BitSize), "only supported 32/64-bits"); in GenerateCalleeSavedRegs()
46 RegOperand &calleeReg = cgFunc.GetOpndBuilder()->CreatePReg(reg, regSize, regType); in GenerateCalleeSavedRegs()
49 MemOperand &memOpnd = cgFunc.GetOpndBuilder()->CreateMem(baseReg, offset, regSize); in GenerateCalleeSavedRegs()
51 GeneratePushCalleeSavedRegs(calleeReg, memOpnd, regSize); in GenerateCalleeSavedRegs()
53 GeneratePopCalleeSavedRegs(calleeReg, memOpnd, regSize); in GenerateCalleeSavedRegs()
65 void X64GenProEpilog::GeneratePushCalleeSavedRegs(RegOperand &regOpnd, MemOperand &memOpnd, uint32 regSize) in GeneratePushCalleeSavedRegs() argument
67 MOperator mMovrmOp = (regSize == k32BitSize) ? x64::MOP_movl_r_m : x64::MOP_movq_r_m; in GeneratePushCalleeSavedRegs()
73 void X64GenProEpilog::GeneratePopCalleeSavedRegs(RegOperand &regOpnd, MemOperand &memOpnd, uint32 regSize) in GeneratePopCalleeSavedRegs() argument
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H A Dx64_reg_info.cpp74 Insn *X64RegInfo::BuildStrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) in BuildStrInsn() argument
77 switch (regSize) { in BuildStrInsn()
100 Insn *X64RegInfo::BuildLdrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) in BuildLdrInsn() argument
103 switch (regSize) { in BuildLdrInsn()
H A Delf_assembler.cpp446 uint8 regSize = GetRegSize(reg); in OpImmAndReg() local
447 if (regSize == k8Bits) { in OpImmAndReg()
450 if (immBit == k16Bits && (regSize == k64Bits || regSize == k32Bits)) { in OpImmAndReg()
454 if (GetRegId(reg) == 0 && (regSize == immBit || (regSize == k64Bits && immBit == k32Bits))) { in OpImmAndReg()
463 uint8 tmp = immBit < std::min(static_cast<uint32>(regSize), 32U) ? 2 : 0; in OpImmAndReg()
1302 uint8 regSize = GetRegSize(reg); in Mov() local
1304 uint8 code = 0xB0 | ((regSize == k8Bits ? 0 : 1) << kLeftShift3Bits); in Mov()
1311 if (regSize in Mov()
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/
H A Daarch64_reg_info.cpp90 Insn *AArch64RegInfo::BuildStrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) in BuildStrInsn() argument
93 return &a64CGFunc->GetInsnBuilder()->BuildInsn(a64CGFunc->PickStInsn(regSize, stype), phyOpnd, memOpnd); in BuildStrInsn()
96 Insn *AArch64RegInfo::BuildLdrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) in BuildLdrInsn() argument
99 return &a64CGFunc->GetInsnBuilder()->BuildInsn(a64CGFunc->PickLdInsn(regSize, stype), phyOpnd, memOpnd); in BuildLdrInsn()
H A Daarch64_obj_emitter.cpp750 uint32 regSize = insn.GetDesc()->GetOpndDes(kInsnSecondOpnd)->GetSize();
752 opnd |= ((regSize == k64BitSize ? 0b11 : 0b10) << kShiftThirteen); // option
1121 uint32 regSize = insn.GetDesc()->GetOpndDes(kInsnFirstOpnd)->GetSize();
1124 CHECK_FATAL((shift == k0BitSize) || (regSize == k16BitSize && shift == k1BitSize) ||
1125 (regSize == k32BitSize && shift == k2BitSize) ||
1126 (regSize == k64BitSize && shift == k3BitSize) || (regSize == k128BitSize && shift == k4BitSize),
H A Daarch64_peep.cpp428 const uint32 regSize = insn.GetDesc()->GetOpndDes(kInsnFirstOpnd)->GetSize(); in OptimizeAddrBOrXShiftExtend() local
432 if ((shift == k0BitSize) || (regSize == k32BitSize && shift == k2BitSize) || in OptimizeAddrBOrXShiftExtend()
433 (regSize == k64BitSize && shift == k3BitSize)) { in OptimizeAddrBOrXShiftExtend()
H A Daarch64_cgfunc.cpp699 uint32 regSize = GetPrimTypeBitSize(rhsPType); in SelectDassign() local
702 regSize, IsSignedInteger(type->GetPrimType())); in SelectDassign()
931 uint32 regSize = GetPrimTypeSize(expr.GetPrimType()); in SelectIread() local
932 if (regSize < k4ByteSize) { in SelectIread()
933 regSize = k4ByteSize; /* 32-bit */ in SelectIread()
937 if (parent.GetOpCode() == OP_eval && regSize <= regSizeMax) { in SelectIread()
938 /* regSize << 3, that is regSize * 8, change bytes to bits */ in SelectIread()
939 result = &GetZeroOpnd(regSize << 3); in SelectIread()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/
H A Dx64_proepilog.h36 void GeneratePushCalleeSavedRegs(RegOperand &regOpnd, MemOperand &memOpnd, uint32 regSize);
37 void GeneratePopCalleeSavedRegs(RegOperand &regOpnd, MemOperand &memOpnd, uint32 regSize);
H A Dx64_reg_info.h39 Insn *BuildStrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) override;
40 Insn *BuildLdrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) override;
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/
H A Dreg_alloc_lsra.cpp389 void LSRALinearScanRegAllocator::SetupLiveInterval(Operand &opnd, Insn &insn, bool isDef, uint32 &nUses, uint32 regSize) in SetupLiveInterval() argument
451 li->SetMaxDefSize(std::max(regSize, li->GetMaxDefSize())); in SetupLiveInterval()
453 li->SetMaxUseSize(std::max(regSize, li->GetMaxUseSize())); in SetupLiveInterval()
672 : regOpnd(opnd), regSize(size), opndIdx(idx), isDef(def) in RegOpndInfo()
676 uint32 regSize = 0; member
695 auto regSize = (regOpnd.GetRegisterType() == kRegTyInt ? opndDesc->GetSize() : regOpnd.GetSize()); in ComputeLiveIntervalForEachOperand() local
696 allRegOpndInfo.emplace_back(regOpnd, regSize, i, !isUse); in ComputeLiveIntervalForEachOperand()
718 SetupLiveInterval(regOpndInfo.regOpnd, insn, false, numUses, regOpndInfo.regSize); in ComputeLiveIntervalForEachOperand()
724 SetupLiveInterval(regOpndInfo.regOpnd, insn, true, numUses, regOpndInfo.regSize); in ComputeLiveIntervalForEachOperand()
782 auto regSize in ComputeLiveIntervalForCall() local
789 auto regSize = opnd->GetSize(); ComputeLiveIntervalForCall() local
1161 uint32 regSize = rli->GetSpillSize(); InsertCallerSave() local
1281 uint32 regSize = li->GetSpillSize(); SpillOperand() local
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/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
H A Daarch64_reg_info.h137 Insn *BuildStrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) override;
138 Insn *BuildLdrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) override;
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
H A Dassembler_aarch64.cpp388 unsigned int regSize = rd.IsW() ? RegWSize : RegXSize; in Mov() local
389 unsigned int halfWords = regSize / HWORDSIZE; in Mov()
391 for (unsigned int shift = 0; shift < regSize; shift += HWORDSIZE) { in Mov()
405 uint64_t realImm = immValue << (RegXSize - regSize) >> (RegXSize - regSize); in Mov()
406 LogicalImmediate orrImm = LogicalImmediate::Create(realImm, regSize); in Mov()
416 ASSERT_PRINT(regSize == RegXSize, "all 32-bit Immediate will be transformed with a MOVZ/MOVK pair"); in Mov()
418 for (unsigned int shift = 0; shift < regSize; shift += HWORDSIZE) { in Mov()
424 LogicalImmediate zeroImm = LogicalImmediate::Create(zeroChunk, regSize); in Mov()
425 LogicalImmediate oneImm = LogicalImmediate::Create(oneChunk, regSize); in Mov()
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/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/
H A Dtarget.h58 size_t regSize = reg.GetSize(); in VixlRegCaseScalar() local
59 if (regSize < WORD_SIZE) { in VixlRegCaseScalar()
60 regSize = WORD_SIZE; in VixlRegCaseScalar()
62 if (regSize > DOUBLE_WORD_SIZE) { in VixlRegCaseScalar()
63 regSize = DOUBLE_WORD_SIZE; in VixlRegCaseScalar()
65 auto vixlReg = vixl::aarch64::Register(reg.GetId(), regSize); in VixlRegCaseScalar()
H A Dencode.cpp122 size_t regSize = reg.GetSize(); in VixlShift() local
123 if (regSize < WORD_SIZE) { in VixlShift()
124 regSize = WORD_SIZE; in VixlShift()
126 auto vixlReg = vixl::aarch64::Register(reg.GetId(), regSize); in VixlShift()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/
H A Dreg_info.h257 virtual Insn *BuildStrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) = 0;
258 virtual Insn *BuildLdrInsn(uint32 regSize, PrimType stype, RegOperand &phyOpnd, MemOperand &memOpnd) = 0;
H A Dreg_alloc_lsra.h406 void SetupLiveInterval(Operand &opnd, Insn &insn, bool isDef, uint32 &nUses, uint32 regSize);
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/x86_64/assembler/
H A Delf_assembler.h465 uint8 regSize = reg == ERR ? k64Bits : GetRegSize(reg); in HasAddrSizePrefix() local
466 return regSize == k32Bits ? true : false; in HasAddrSizePrefix()
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/
H A Dencode.cpp148 size_t regSize = size == 0 ? reg.GetSize() : size; in ArchReg() local
152 switch (regSize) { in ArchReg()

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