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Searched refs:isFp (Results 1 - 22 of 22) sorted by relevance

/arkcompiler/runtime_core/static_core/libpandabase/utils/
H A Darch.h208 constexpr RegMask GetCallerRegsMask(Arch arch, bool isFp) in GetCallerRegsMask() argument
212 return isFp ? ArchTraits<Arch::AARCH32>::CALLER_FP_REG_MASK : ArchTraits<Arch::AARCH32>::CALLER_REG_MASK; in GetCallerRegsMask()
214 return isFp ? ArchTraits<Arch::AARCH64>::CALLER_FP_REG_MASK : ArchTraits<Arch::AARCH64>::CALLER_REG_MASK; in GetCallerRegsMask()
216 return isFp ? ArchTraits<Arch::X86>::CALLER_FP_REG_MASK : ArchTraits<Arch::X86>::CALLER_REG_MASK; in GetCallerRegsMask()
218 return isFp ? ArchTraits<Arch::X86_64>::CALLER_FP_REG_MASK : ArchTraits<Arch::X86_64>::CALLER_REG_MASK; in GetCallerRegsMask()
224 constexpr RegMask GetCalleeRegsMask(Arch arch, bool isFp, bool irtocOptimized = false) in GetCalleeRegsMask() argument
228 return isFp ? ArchTraits<Arch::AARCH32>::CALLEE_FP_REG_MASK : ArchTraits<Arch::AARCH32>::CALLEE_REG_MASK; in GetCalleeRegsMask()
230 // return AARCH64Case(arch, isFp, irtocOptimized) in GetCalleeRegsMask()
235 return isFp ? irtocOptimized ? ArchTraits<Arch::AARCH64>::IRTOC_OPTIMIZED_CALLEE_FP_REG_MASK in GetCalleeRegsMask()
240 return isFp in GetCalleeRegsMask()
248 GetFirstCalleeReg(Arch arch, bool isFp) GetFirstCalleeReg() argument
259 GetLastCalleeReg(Arch arch, bool isFp) GetLastCalleeReg() argument
268 GetCalleeRegsCount(Arch arch, bool isFp) GetCalleeRegsCount() argument
273 GetFirstCallerReg(Arch arch, bool isFp) GetFirstCallerReg() argument
278 GetLastCallerReg(Arch arch, bool isFp) GetLastCallerReg() argument
283 GetCallerRegsCount(Arch arch, bool isFp) GetCallerRegsCount() argument
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H A Dcframe_layout.h226 constexpr size_t GetCalleeFirstSlot(bool isFp) const in GetCalleeFirstSlot()
228 return isFp ? GetCalleeRegistersCount(false) : 0; in GetCalleeFirstSlot()
231 constexpr size_t GetCalleeLastSlot(bool isFp) const in GetCalleeLastSlot()
233 return GetCalleeFirstSlot(isFp) + GetCalleeRegistersCount(isFp) - 1; in GetCalleeLastSlot()
236 constexpr size_t GetCallerFirstSlot(bool isFp) const in GetCallerFirstSlot()
238 return GetCalleeLastSlot(true) + 1 + (isFp ? GetCallerRegistersCount(false) : 0); in GetCallerFirstSlot()
241 constexpr size_t GetCallerLastSlot(bool isFp) const in GetCallerLastSlot()
243 return GetCallerFirstSlot(isFp) + GetCallerRegistersCount(isFp) in GetCallerLastSlot()
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/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/
H A Dtarget_info.h136 static constexpr const char *GetRegName(size_t reg, bool isFp)
138 ASSERT(reg < REG_NAMES.size() || isFp);
139 ASSERT(reg < FP_REG_NAMES.size() || !isFp);
140 return isFp ? FP_REG_NAMES[reg] : REG_NAMES[reg];
167 static constexpr const char *GetRegName(size_t reg, bool isFp)
169 ASSERT(reg < REG_NAMES.size() || isFp);
170 ASSERT(reg < FP_REG_NAMES.size() || !isFp);
171 return isFp ? FP_REG_NAMES[reg] : REG_NAMES[reg];
198 static constexpr const char *GetRegName(size_t reg, bool isFp)
200 ASSERT(reg < REG_NAMES.size() || isFp);
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H A Dencode.h330 virtual void SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
331 virtual void LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
351 virtual void SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask);
352 virtual void LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask);
355 virtual void PushRegisters(RegMask registers, bool isFp);
356 virtual void PopRegisters(RegMask registers, bool isFp);
H A Dencode.cpp587 [[maybe_unused]] size_t startReg, [[maybe_unused]] bool isFp) in SaveRegisters()
593 [[maybe_unused]] size_t startReg, [[maybe_unused]] bool isFp) in LoadRegisters()
598 void Encoder::SaveRegisters([[maybe_unused]] RegMask registers, [[maybe_unused]] bool isFp, in SaveRegisters() argument
604 void Encoder::LoadRegisters([[maybe_unused]] RegMask registers, [[maybe_unused]] bool isFp, in LoadRegisters() argument
633 void Encoder::PushRegisters([[maybe_unused]] RegMask registers, [[maybe_unused]] bool isFp) in PushRegisters() argument
638 void Encoder::PopRegisters([[maybe_unused]] RegMask registers, [[maybe_unused]] bool isFp) in PopRegisters() argument
586 SaveRegisters([[maybe_unused]] RegMask registers, [[maybe_unused]] ssize_t slot, [[maybe_unused]] size_t startReg, [[maybe_unused]] bool isFp) SaveRegisters() argument
592 LoadRegisters([[maybe_unused]] RegMask registers, [[maybe_unused]] ssize_t slot, [[maybe_unused]] size_t startReg, [[maybe_unused]] bool isFp) LoadRegisters() argument
H A Dcodegen.cpp1037 bool isFp = (location.GetKind() == LocationType::FP_REGISTER); in CreateVRegForRegister() local
1039 auto reg = Reg(regNum, isFp ? FLOAT64_TYPE : INT64_TYPE); in CreateVRegForRegister()
1043 if (isFp) { in CreateVRegForRegister()
1054 ASSERT(regNum >= GetFirstCallerReg(GetArch(), isFp)); in CreateVRegForRegister()
1055 auto lastSlot = GetFrameLayout().GetCallerLastSlot(isFp); in CreateVRegForRegister()
1056 RegMask mask(GetCallerRegsMask(GetArch(), isFp)); in CreateVRegForRegister()
/arkcompiler/runtime_core/static_core/runtime/include/
H A Dcframe.h276 SlotType ReadCalleeSavedRegister(size_t reg, bool isFp, SlotType **calleeStack) const in ReadCalleeSavedRegister() argument
278 ASSERT(reg >= GetFirstCalleeReg(ARCH, isFp)); in ReadCalleeSavedRegister()
279 ASSERT(reg <= GetLastCalleeReg(ARCH, isFp)); in ReadCalleeSavedRegister()
280 ASSERT(GetCalleeRegsCount(ARCH, isFp) != 0); in ReadCalleeSavedRegister()
281 size_t startSlot = GetCalleeRegsMask(ARCH, isFp).GetDistanceFromTail(reg); in ReadCalleeSavedRegister()
282 if (isFp) { in ReadCalleeSavedRegister()
291 void WriteCalleeSavedRegister(size_t reg, SlotType value, bool isFp, SlotType **calleeStack) const in WriteCalleeSavedRegister() argument
293 ASSERT(reg >= GetFirstCalleeReg(ARCH, isFp)); in WriteCalleeSavedRegister()
294 ASSERT(reg <= GetLastCalleeReg(ARCH, isFp)); in WriteCalleeSavedRegister()
295 ASSERT(GetCalleeRegsCount(ARCH, isFp) ! in WriteCalleeSavedRegister()
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/arkcompiler/runtime_core/static_core/runtime/
H A Dcframe.cpp99 bool isFp = vreg.GetLocation() == VRegInfo::Location::FP_REGISTER; in GetVRegValueRegister() local
100 if ((GetCallerRegsMask(ARCH, isFp) & (1U << vreg.GetValue())).Any()) { in GetVRegValueRegister()
102 RegMask mask(GetCallerRegsMask(RUNTIME_ARCH, isFp)); in GetVRegValueRegister()
104 regNum = fl.GetCallerLastSlot(isFp) - regNum; in GetVRegValueRegister()
121 uint64_t val = ReadCalleeSavedRegister(vreg.GetValue(), isFp, calleeStack); in GetVRegValueRegister()
123 val |= static_cast<uint64_t>(ReadCalleeSavedRegister(vreg.GetValue() + 1, isFp, calleeStack)) in GetVRegValueRegister()
130 if (isFp) { in GetVRegValueRegister()
174 bool isFp = vreg.GetLocation() == VRegInfo::Location::FP_REGISTER; in SetVRegValue() local
175 if ((GetCallerRegsMask(ARCH, isFp) & (1U << vreg.GetValue())).Any()) { in SetVRegValue()
177 auto regNum = locationValue - static_cast<int>(GetFirstCallerReg(ARCH, isFp)); in SetVRegValue()
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/arkcompiler/runtime_core/static_core/irtoc/backend/compiler/
H A Dcodegen_fastpath.cpp22 static void SaveCallerRegistersInFrame(RegMask mask, Encoder *encoder, const CFrameLayout &fl, bool isFp) in SaveCallerRegistersInFrame() argument
29 mask &= GetCallerRegsMask(fl.GetArch(), isFp); in SaveCallerRegistersInFrame()
30 auto startSlot = fl.GetStackStartSlot() + fl.GetCallerLastSlot(isFp); in SaveCallerRegistersInFrame()
31 encoder->SaveRegisters(mask, isFp, -startSlot, fpReg, GetCallerRegsMask(fl.GetArch(), isFp)); in SaveCallerRegistersInFrame()
34 static void RestoreCallerRegistersFromFrame(RegMask mask, Encoder *encoder, const CFrameLayout &fl, bool isFp) in RestoreCallerRegistersFromFrame() argument
41 mask &= GetCallerRegsMask(fl.GetArch(), isFp); in RestoreCallerRegistersFromFrame()
42 auto startSlot = fl.GetStackStartSlot() + fl.GetCallerLastSlot(isFp); in RestoreCallerRegistersFromFrame()
43 encoder->LoadRegisters(mask, isFp, -startSlot, fpReg, GetCallerRegsMask(fl.GetArch(), isFp)); in RestoreCallerRegistersFromFrame()
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/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/
H A Dtarget.h412 void SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) override;
413 void LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) override;
414 void SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) override;
415 void LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) override;
416 void PushRegisters(RegMask registers, bool isFp) override;
417 void PopRegisters(RegMask registers, bool isFp) override;
435 void LoadStoreRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
437 void LoadStoreRegisters(RegMask registers, ssize_t slot, Reg base, RegMask mask, bool isFp);
439 void LoadStoreRegistersMainLoop(RegMask registers, ssize_t slot, Reg base, RegMask mask, bool isFp);
441 void ConstructLdrStr(vixl::aarch32::MemOperand mem, size_t i, bool isFp);
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H A Dregfile.cpp204 bool isFp = reg.IsFloat(); in IsCalleeRegister() local
205 return reg.GetId() >= GetFirstCalleeReg(Arch::AARCH32, isFp) && in IsCalleeRegister()
206 reg.GetId() <= GetLastCalleeReg(Arch::AARCH32, isFp); in IsCalleeRegister()
H A Dencode.cpp330 void Aarch32Encoder::SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) in SaveRegisters() argument
332 LoadStoreRegisters<true>(registers, slot, startReg, isFp); in SaveRegisters()
334 void Aarch32Encoder::LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) in LoadRegisters() argument
336 LoadStoreRegisters<false>(registers, slot, startReg, isFp); in LoadRegisters()
339 void Aarch32Encoder::SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) in SaveRegisters() argument
341 LoadStoreRegisters<true>(registers, slot, base, mask, isFp); in SaveRegisters()
343 void Aarch32Encoder::LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) in LoadRegisters() argument
345 LoadStoreRegisters<false>(registers, slot, base, mask, isFp); in LoadRegisters()
3163 void Aarch32Encoder::LoadStoreRegistersMainLoop(RegMask registers, ssize_t slot, Reg base, RegMask mask, bool isFp) in LoadStoreRegistersMainLoop() argument
3184 ConstructLdrStr<IS_STORE>(mem, i, isFp); in LoadStoreRegistersMainLoop()
3189 LoadStoreRegisters(RegMask registers, ssize_t slot, Reg base, RegMask mask, bool isFp) LoadStoreRegisters() argument
3206 ConstructLdrStr(vixl::aarch32::MemOperand mem, size_t i, bool isFp) ConstructLdrStr() argument
3225 ConstructAddForBigOffset(vixl::aarch32::Register tmp, vixl::aarch32::Register *baseReg, ssize_t *slot, ssize_t maxOffset, bool isFp) ConstructAddForBigOffset() argument
3244 LoadStoreRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) LoadStoreRegisters() argument
3270 PushRegisters(RegMask registers, bool isFp) PushRegisters() argument
3277 PopRegisters(RegMask registers, bool isFp) PopRegisters() argument
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/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/
H A Dtarget.h420 void SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) override;
421 void LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) override;
422 void SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) override;
423 void LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) override;
424 void PushRegisters(RegMask registers, bool isFp) override;
425 void PopRegisters(RegMask registers, bool isFp) override;
433 void LoadStoreRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
436 void LoadStoreRegistersLoop(RegMask registers, ssize_t slot, size_t startReg, bool isFp,
440 void LoadStoreRegisters(RegMask registers, bool isFp, int32_t slot, Reg base, RegMask mask);
443 void LoadStoreRegistersMainLoop(RegMask registers, bool isFp, int32_
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H A Dregfile.cpp136 bool isFp = reg.IsFloat(); in IsCalleeRegister() local
137 return reg.GetId() >= GetFirstCalleeReg(Arch::AARCH64, isFp) && in IsCalleeRegister()
138 reg.GetId() <= GetLastCalleeReg(Arch::AARCH64, isFp); in IsCalleeRegister()
H A Dencode.cpp3049 void Aarch64Encoder::LoadStoreRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) in LoadStoreRegisters() argument
3075 LoadStoreRegistersLoop<IS_STORE>(registers, slot, startReg, isFp, tmp); in LoadStoreRegisters()
3077 LoadStoreRegistersLoop<IS_STORE>(registers, slot, startReg, isFp, vixl::aarch64::sp); in LoadStoreRegisters()
3106 void Aarch64Encoder::LoadStoreRegistersMainLoop(RegMask registers, bool isFp, int32_t slot, Reg base, RegMask mask) in LoadStoreRegistersMainLoop() argument
3134 CPURegister(lastId, vixl::aarch64::kXRegSize, isFp ? CPURegister::kVRegister : CPURegister::kRegister); in LoadStoreRegistersMainLoop()
3137 CPURegister(id, vixl::aarch64::kXRegSize, isFp ? CPURegister::kVRegister : CPURegister::kRegister); in LoadStoreRegistersMainLoop()
3148 CPURegister(lastId, vixl::aarch64::kXRegSize, isFp ? CPURegister::kVRegister : CPURegister::kRegister); in LoadStoreRegistersMainLoop()
3154 void Aarch64Encoder::LoadStoreRegisters(RegMask registers, bool isFp, int32_t slot, Reg base, RegMask mask) in LoadStoreRegisters() argument
3181 LoadStoreRegistersMainLoop<IS_STORE>(registers, isFp, slot, base, mask); in LoadStoreRegisters()
3185 void Aarch64Encoder::LoadStoreRegistersLoop(RegMask registers, ssize_t slot, size_t startReg, bool isFp, in LoadStoreRegistersLoop() argument
3223 SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) SaveRegisters() argument
3228 LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) LoadRegisters() argument
3233 SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) SaveRegisters() argument
3238 LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) LoadRegisters() argument
3243 PushRegisters(RegMask registers, bool isFp) PushRegisters() argument
3276 PopRegisters(RegMask registers, bool isFp) PopRegisters() argument
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/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/
H A Dregfile.cpp117 bool isFp = reg.IsFloat(); in IsCalleeRegister() local
118 return reg.GetId() >= GetFirstCalleeReg(Arch::X86_64, isFp) && reg.GetId() <= GetLastCalleeReg(Arch::X86_64, isFp); in IsCalleeRegister()
H A Dtarget.h408 void SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) override;
409 void LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) override;
410 void SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) override;
411 void LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) override;
412 void PushRegisters(RegMask registers, bool isFp) override;
413 void PopRegisters(RegMask registers, bool isFp) override;
424 void LoadStoreRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp);
427 void LoadStoreRegisters(RegMask registers, bool isFp, int32_t slot, Reg base, RegMask mask);
H A Dencode.cpp3090 void Amd64Encoder::LoadStoreRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) in LoadStoreRegisters() argument
3100 if (isFp) { in LoadStoreRegisters()
3106 if (isFp) { in LoadStoreRegisters()
3116 void Amd64Encoder::LoadStoreRegisters(RegMask registers, bool isFp, int32_t slot, Reg base, RegMask mask) in LoadStoreRegisters() argument
3141 if (isFp) { in LoadStoreRegisters()
3147 if (isFp) { in LoadStoreRegisters()
3156 void Amd64Encoder::SaveRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) in SaveRegisters() argument
3158 LoadStoreRegisters<true>(registers, slot, startReg, isFp); in SaveRegisters()
3161 void Amd64Encoder::LoadRegisters(RegMask registers, ssize_t slot, size_t startReg, bool isFp) in LoadRegisters() argument
3163 LoadStoreRegisters<false>(registers, slot, startReg, isFp); in LoadRegisters()
3166 SaveRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) SaveRegisters() argument
3171 LoadRegisters(RegMask registers, bool isFp, ssize_t slot, Reg base, RegMask mask) LoadRegisters() argument
3176 PushRegisters(RegMask registers, bool isFp) PushRegisters() argument
3190 PopRegisters(RegMask registers, bool isFp) PopRegisters() argument
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/arkcompiler/runtime_core/static_core/compiler/optimizer/optimizations/regalloc/
H A Dreg_alloc_graph_coloring.cpp451 bool isFp = DataType::IsFloatType(interval->GetType()); in InitWorkingRanges() local
452 auto *ranges = isFp ? fpRanges : generalRanges; in InitWorkingRanges()
454 auto mask = isFp ? GetVRegMask() : GetRegMask(); in InitWorkingRanges()
H A Dreg_alloc_linear_scan.cpp92 bool isFp = DataType::IsFloatType(interval->GetType()); in PrepareInterval() local
93 auto &intervals = isFp ? GetIntervals<true>() : GetIntervals<false>(); in PrepareInterval()
/arkcompiler/runtime_core/static_core/irtoc/backend/
H A Dcompilation.cpp36 RegMask &GetUsedRegs(bool isFp) in GetUsedRegs() argument
38 return isFp ? vregMask_ : regMask_; in GetUsedRegs()
/arkcompiler/runtime_core/static_core/compiler/code_info/
H A Dcode_info.h292 uint32_t GetSavedCalleeRegsMask(bool isFp) const in GetSavedCalleeRegsMask()
294 return isFp ? GetHeader().GetCalleeFpRegMask() : GetHeader().GetCalleeRegMask(); in GetSavedCalleeRegsMask()

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