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Searched refs:bitPos (Results 1 - 14 of 14) sorted by relevance

/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/mempool/include/
H A Dmaple_sparse_bitvector.h73 unsigned bitPos = 0; in ConvertToSet() local
76 bitPos += trailingZeroNum; in ConvertToSet()
80 res.insert(base + bitPos + i * kBitWordSize); in ConvertToSet()
89 unsigned bitPos = 0; in ConvertToSet() local
92 bitPos += trailingZeroNum; in ConvertToSet()
95 res.insert(base + bitPos + i * kBitWordSize); in ConvertToSet()
/arkcompiler/ets_frontend/es2panda/util/
H A Dhelpers.cpp197 uint32_t bitPos = 0; in GetIntegerSignificandBitCount() local
204 bitPos = (minBitPos + maxBitPos) / 2; // 2: binary search in GetIntegerSignificandBitCount()
205 GetScientificNotationForDouble(number, bitPos, numberBitCount, significandArray, in GetIntegerSignificandBitCount()
208 // Update bitPos in GetIntegerSignificandBitCount()
210 while (bitPos >= integerAndPointBitCount && significandArray[bitPos] == '0') { in GetIntegerSignificandBitCount()
211 bitPos--; in GetIntegerSignificandBitCount()
213 maxBitPos = bitPos; in GetIntegerSignificandBitCount()
215 minBitPos = bitPos + 1; in GetIntegerSignificandBitCount()
220 bitPos in GetIntegerSignificandBitCount()
[all...]
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
H A Dassembler_aarch64.h345 void Tbz(const Register &rt, int32_t bitPos, Label *label);
346 void Tbz(const Register &rt, int32_t bitPos, int32_t imm);
347 void Tbnz(const Register &rt, int32_t bitPos, Label *label);
348 void Tbnz(const Register &rt, int32_t bitPos, int32_t imm);
H A Dassembler_aarch64.cpp988 void AssemblerAarch64::Tbz(const Register &rt, int32_t bitPos, Label *label) in Tbz() argument
993 Tbz(rt, bitPos, offsetImm); in Tbz()
996 void AssemblerAarch64::Tbz(const Register &rt, int32_t bitPos, int32_t imm) in Tbz() argument
998 uint32_t b5 = (bitPos << (BRANCH_B5_LOWBITS - 5)) & BRANCH_B5_MASK; in Tbz()
999 uint32_t b40 = (bitPos << BRANCH_B40_LOWBITS) & BRANCH_B40_MASK; in Tbz()
1005 void AssemblerAarch64::Tbnz(const Register &rt, int32_t bitPos, Label *label) in Tbnz() argument
1010 Tbnz(rt, bitPos, offsetImm); in Tbnz()
1013 void AssemblerAarch64::Tbnz(const Register &rt, int32_t bitPos, int32_t imm) in Tbnz() argument
1015 uint32_t b5 = (bitPos << (BRANCH_B5_LOWBITS - 5)) & BRANCH_B5_MASK; in Tbnz()
1016 uint32_t b40 = (bitPos << BRANCH_B40_LOWBIT in Tbnz()
[all...]
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/
H A Daarch64_fixshortbranch.cpp140 auto &bitPos = static_cast<ImmOperand &>(insn->GetOperand(kInsnSecondOpnd)); in FixShortBranches() local
168 cgFunc->GetInsnBuilder()->BuildInsn(ubfxOp, tmp, reg, bitPos, bitSize)); in FixShortBranches()
H A Daarch64_peep.cpp1860 ImmOperand &bitPos = aarch64CGFunc->CreateImmOperand(n, k8BitSize, false); in Run() local
1862 Insn &ubfxInsn = cgFunc.GetInsnBuilder()->BuildInsn(ubfxOp, dstReg, srcReg, bitPos, bitSize); in Run()
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/
H A Dencode.h414 virtual void EncodeBitTestAndBranch(LabelHolder::LabelId id, Reg reg, uint32_t bitPos, bool bitValue);
H A Dencode.cpp767 [[maybe_unused]] compiler::Reg reg, [[maybe_unused]] uint32_t bitPos, in EncodeBitTestAndBranch()
766 EncodeBitTestAndBranch([[maybe_unused]] compiler::LabelHolder::LabelId id, [[maybe_unused]] compiler::Reg reg, [[maybe_unused]] uint32_t bitPos, [[maybe_unused]] bool bitValue) EncodeBitTestAndBranch() argument
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/
H A Dencode.cpp449 void Aarch32Encoder::EncodeBitTestAndBranch(LabelHolder::LabelId id, Reg reg, uint32_t bitPos, bool bitValue) in EncodeBitTestAndBranch() argument
451 ASSERT(reg.IsScalar() && reg.GetSize() > bitPos); in EncodeBitTestAndBranch()
454 if (bitPos < WORD_SIZE) { in EncodeBitTestAndBranch()
455 GetMasm()->tst(VixlReg(reg), VixlImm(1U << bitPos)); in EncodeBitTestAndBranch()
457 GetMasm()->tst(VixlRegU(reg), VixlImm(1U << (bitPos - WORD_SIZE))); in EncodeBitTestAndBranch()
460 GetMasm()->tst(VixlReg(reg), VixlImm(1U << bitPos)); in EncodeBitTestAndBranch()
H A Dtarget.h406 void EncodeBitTestAndBranch(LabelHolder::LabelId id, compiler::Reg reg, uint32_t bitPos, bool bitValue) override;
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/
H A Dtarget.h412 void EncodeBitTestAndBranch(LabelHolder::LabelId id, compiler::Reg reg, uint32_t bitPos, bool bitValue) override;
H A Dencode.cpp408 void Aarch64Encoder::EncodeBitTestAndBranch(LabelHolder::LabelId id, compiler::Reg reg, uint32_t bitPos, bool bitValue) in EncodeBitTestAndBranch() argument
410 ASSERT(reg.IsScalar() && reg.GetSize() > bitPos); in EncodeBitTestAndBranch()
413 GetMasm()->Tbnz(VixlReg(reg), bitPos, label); in EncodeBitTestAndBranch() local
415 GetMasm()->Tbz(VixlReg(reg), bitPos, label); in EncodeBitTestAndBranch() local
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/
H A Dtarget.h402 void EncodeBitTestAndBranch(LabelHolder::LabelId id, compiler::Reg reg, uint32_t bitPos, bool bitValue) override;
H A Dencode.cpp562 void Amd64Encoder::EncodeBitTestAndBranch(LabelHolder::LabelId id, compiler::Reg reg, uint32_t bitPos, bool bitValue) in EncodeBitTestAndBranch() argument
564 ASSERT(reg.IsScalar() && reg.GetSize() > bitPos); in EncodeBitTestAndBranch()
568 GetMasm()->mov(ArchReg(tmpReg), asmjit::imm(static_cast<uint64_t>(1) << bitPos)); in EncodeBitTestAndBranch()
571 GetMasm()->test(ArchReg(reg), asmjit::imm(1U << bitPos)); in EncodeBitTestAndBranch()

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