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Searched refs:baseReg (Results 1 - 21 of 21) sorted by relevance

/arkcompiler/ets_runtime/ecmascript/compiler/assembler/x64/
H A Dmacro_assembler_x64.cpp24 x64::Register baseReg = (dstStackSlot.IsFrameBase()) ? x64::rbp : x64::rsp; in Move() local
25 x64::Operand dstOpnd(baseReg, dstStackSlot.GetOffset()); in Move()
43 x64::Register baseReg = (stackSlot.IsFrameBase()) ? x64::rbp : x64::rsp; in Cmp() local
44 x64::Operand opnd(baseReg, stackSlot.GetOffset()); in Cmp()
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/
H A Dmacro_assembler.h41 StackSlotOperand(BaseRegister baseReg, int32_t stackOffset) in StackSlotOperand() argument
42 : baseRegister(baseReg), offset(stackOffset) {} in StackSlotOperand()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/
H A Daarch64_insn.cpp130 auto *baseReg = v->GetBaseRegister(); in Visit() local
131 DEBUG_ASSERT(baseReg != nullptr, "expect an RegOperand here"); in Visit()
132 uint32 baseSize = baseReg->GetSize(); in Visit()
134 baseReg->SetSize(k64BitSize); in Visit()
136 EmitIntReg(*baseReg); in Visit()
137 baseReg->SetSize(baseSize); in Visit()
187 auto *baseReg = v->GetBaseRegister(); in Visit() local
189 baseReg->SetSize(k64BitSize); in Visit()
191 EmitIntReg(*baseReg); in Visit()
H A Daarch64_obj_emitter.cpp1172 Operand *baseReg = memOpnd.GetBaseRegister();
1173 binInsn |= GetOpndMachineValue(*baseReg) << kShiftFive;
1200 GetOpndMachineValue(insn.GetOperand(kInsnFirstOpnd)) | (GetOpndMachineValue(*baseReg) << kShiftFive);
1224 Operand *baseReg = memOpnd.GetBaseRegister();
1226 opnd |= GetOpndMachineValue(*baseReg) << kShiftFive;
1238 Operand *baseReg = memOpnd.GetBaseRegister();
1240 opnd |= GetOpndMachineValue(*baseReg) << kShiftFive;
1254 Operand *baseReg = memOpnd.GetBaseRegister();
1256 opnd |= GetOpndMachineValue(*baseReg) << kShiftFive;
1270 Operand *baseReg
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H A Daarch64_cgfunc.cpp571 MemOperand &AArch64CGFunc::CreateReplacementMemOperand(uint32 bitLen, RegOperand &baseReg, int64 offset) in CreateReplacementMemOperand() argument
573 return CreateMemOpnd(baseReg, offset, bitLen); in CreateReplacementMemOperand()
1414 CHECK_FATAL(is64Bits, "baseReg of mem in aarch64 must be 64bit size"); in SelectAdd()
4000 auto *baseReg = SelectRegread(*static_cast<RegreadNode *>(baseExpr));
4002 MemOperand *memOpnd = &GetOrCreateMemOpnd(MemOperand::kAddrModeBOrX, GetPrimTypeBitSize(ptype), baseReg,
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
H A Dmacro_assembler_aarch64.cpp38 aarch64::Register baseReg = (dstStackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in Move() local
40 aarch64::MemoryOperand dstOpnd(baseReg, static_cast<int64_t>(dstStackSlot.GetOffset())); in Move()
60 aarch64::Register baseReg = (stackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in Cmp() local
62 aarch64::MemoryOperand opnd(baseReg, static_cast<int64_t>(stackSlot.GetOffset())); in Cmp()
106 aarch64::Register baseReg = (dstStackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in SaveReturnRegister() local
108 aarch64::MemoryOperand dstOpnd(baseReg, static_cast<int64_t>(dstStackSlot.GetOffset())); in SaveReturnRegister()
/arkcompiler/ets_frontend/es2panda/ir/base/
H A DclassDefinition.cpp111 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
119 pg->StoreAccumulator(this, baseReg); in CompileHeritageClause()
120 return baseReg; in CompileHeritageClause()
393 compiler::VReg baseReg = CompileHeritageClause(pg); in Compile() local
402 pg->DefineClassWithBuffer(this, ctorId, bufIdx, baseReg); in Compile()
685 compiler::VReg baseReg = CompileHeritageClause(pg); in CompileSendableClass() local
691 pg->DefineSendableClass(this, ctorId, bufIdx, baseReg); in CompileSendableClass()
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/
H A Dencode.cpp234 auto baseReg = VixlReg(mem.GetBase()); in ConvertMem() local
241 return vixl::aarch32::MemOperand(baseReg, VixlReg(indexReg), vixl::aarch32::LSL, shift); in ConvertMem()
243 return vixl::aarch32::MemOperand(baseReg, VixlReg(indexReg)); in ConvertMem()
247 return vixl::aarch32::MemOperand(baseReg, offset); in ConvertMem()
249 return vixl::aarch32::MemOperand(baseReg); in ConvertMem()
849 auto baseReg = VixlReg(mem.GetBase()); in PrepareMemLdS() local
851 if (baseReg.IsSP()) { in PrepareMemLdS()
852 GetMasm()->Mov(tmp, baseReg); in PrepareMemLdS()
853 baseReg = tmp; in PrepareMemLdS()
882 return vixl::aarch32::MemOperand(baseReg, VixlRe in PrepareMemLdS()
922 auto baseReg = VixlReg(mem.GetBase()); PrepareMemLdSForFloat() local
3168 vixl::aarch32::Register baseReg = VixlReg(base); LoadStoreRegistersMainLoop() local
3195 vixl::aarch32::Register baseReg = VixlReg(base); LoadStoreRegisters() local
3225 ConstructAddForBigOffset(vixl::aarch32::Register tmp, vixl::aarch32::Register *baseReg, ssize_t *slot, ssize_t maxOffset, bool isFp) ConstructAddForBigOffset() argument
3255 vixl::aarch32::Register baseReg = vixl::aarch32::sp; LoadStoreRegisters() local
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H A Dtarget.h442 void ConstructAddForBigOffset(vixl::aarch32::Register tmp, vixl::aarch32::Register *baseReg, ssize_t *slot,
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/
H A Doperand.cpp166 RegOperand *baseReg = GetBaseRegister(); in Less() local
168 int32 nRet = baseReg->RegCompare(*rbaseReg); in Less()
H A Dreg_alloc_lsra.cpp1007 uint32 baseReg = isInt ? firstIntReg : firstFpReg; in UpdateParamAllocateInfo() local
1024 blockForbiddenMask |= (1UL << (i + baseReg)); in UpdateParamAllocateInfo()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/
H A Dx64_proepilog.cpp39 RegOperand &baseReg = cgFunc.GetOpndBuilder()->CreatePReg(x64::RBP, k64BitSize, kRegTyInt); in GenerateCalleeSavedRegs() local
49 MemOperand &memOpnd = cgFunc.GetOpndBuilder()->CreateMem(baseReg, offset, regSize); in GenerateCalleeSavedRegs()
H A Dx64_MPIsel.cpp430 /* mov .L_xxx_LOCAL_CONST.x(%baseReg, %indexOpnd, 8), %dstRegOpnd */ in SelectRangeGoto()
432 RegOperand &baseReg = cgFunc->GetOpndBuilder()->CreatePReg(x64::RBP, GetPrimTypeBitSize(PTY_i64), kRegTyInt); in SelectRangeGoto() local
433 dstMemOpnd.SetBaseRegister(baseReg); in SelectRangeGoto()
436 dstMemOpnd.SetScaleOperand(cgFunc->GetOpndBuilder()->CreateImm(baseReg.GetSize(), k8ByteSize)); in SelectRangeGoto()
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/
H A Dencode.cpp142 auto baseReg = Reg(mem.GetBase().GetId(), INT64_TYPE); in ConvertMem() local
147 return vixl::aarch64::MemOperand(VixlReg(baseReg), VixlImm(disp)); in ConvertMem()
158 return vixl::aarch64::MemOperand(VixlReg(baseReg), VixlReg(indexReg), vixl::aarch64::Extend::SXTW, scale); in ConvertMem()
163 return vixl::aarch64::MemOperand(VixlReg(baseReg), VixlReg(indexReg), vixl::aarch64::LSL, scale); in ConvertMem()
166 return vixl::aarch64::MemOperand(VixlReg(baseReg), VixlReg(indexReg)); in ConvertMem()
2036 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdr() local
2040 ASSERT(baseReg.GetId() == rzero || !baseReg.IsValid()); in EncodeLdr()
2094 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdrAcquireInvalid() local
2100 ASSERT(baseReg in EncodeLdrAcquireInvalid()
2172 auto baseReg = mem.GetBase(); CheckAlignment() local
3085 auto baseReg = VixlReg(base); LoadStorePair() local
3097 auto baseReg = VixlReg(base); LoadStoreReg() local
3185 LoadStoreRegistersLoop(RegMask registers, ssize_t slot, size_t startReg, bool isFp, const vixl::aarch64::Register &baseReg) LoadStoreRegistersLoop() argument
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H A Dtarget.h437 const vixl::aarch64::Register &baseReg);
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/
H A Dcodegen.h393 void CalculateCardIndex(Reg baseReg, ScopedTmpReg *tmp, ScopedTmpReg *tmp1);
533 void EncodeCalculateCardIndex(Reg baseReg, ScopedTmpReg *tmp, ScopedTmpReg *tmp1);
H A Dcodegen.cpp2810 void PostWriteBarrier::EncodeCalculateCardIndex(Reg baseReg, ScopedTmpReg *tmp, ScopedTmpReg *tmp1) in EncodeCalculateCardIndex() argument
2812 ASSERT(baseReg != INVALID_REGISTER); in EncodeCalculateCardIndex()
2815 if (baseReg.GetSize() < Reg(*tmp).GetSize()) { in EncodeCalculateCardIndex()
2816 tmp->ChangeType(baseReg.GetType()); in EncodeCalculateCardIndex()
2817 tmp1->ChangeType(baseReg.GetType()); in EncodeCalculateCardIndex()
2820 enc->EncodeSub(*tmp, baseReg, *tmp); in EncodeCalculateCardIndex()
/arkcompiler/ets_frontend/ets2panda/compiler/core/
H A DJSCompiler.cpp51 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
59 pg->StoreAccumulator(node, baseReg); in CompileHeritageClause()
60 return baseReg; in CompileHeritageClause()
382 compiler::VReg baseReg = CompileHeritageClause(pg, node); in Compile() local
388 pg->DefineClassWithBuffer(node, ctorId, bufIdx, lexenv, baseReg); in Compile()
/arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/include/cg/aarch64/
H A Daarch64_cgfunc.h423 MemOperand &CreateReplacementMemOperand(uint32 bitLen, RegOperand &baseReg, int64 offset);
/arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/
H A Dencode.cpp3118 auto baseReg = ArchReg(base); in LoadStoreRegisters() local
3138 asmjit::x86::Mem mem = asmjit::x86::ptr(baseReg, (slot + index - 1) * DOUBLE_WORD_SIZE_BYTES); in LoadStoreRegisters()
/arkcompiler/runtime_core/static_core/libllvmbackend/lowering/
H A Dllvm_ir_constructor.cpp1466 std::string baseReg = representable ? "sp" : "x16"; in CreateInterpreterReturnRestoreRegs() local
1486 asmString += baseReg; in CreateInterpreterReturnRestoreRegs()

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