Searched refs:Subs (Results 1 - 5 of 5) sorted by relevance
| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/ |
| H A D | assembler_aarch64.h | 330 void Subs(const Register &rd, const Register &rn, const Operand &operand);
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| H A D | assembler_aarch64.cpp | 826 void AssemblerAarch64::Subs(const Register &rd, const Register &rn, const Operand &operand) in Subs() function in panda::ecmascript::aarch64::AssemblerAarch64
894 Subs(Register(Zero, rd.GetType()), rd, operand); in Cmp()
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/ |
| H A D | encode.cpp | 1805 GetMasm()->Subs(VixlReg(dst), VixlReg(src0), VixlReg(src1)); in EncodeSub()
2156 GetMasm()->Subs(VixlReg(tmpReg), VixlReg(src0), VixlReg(src1)); in EncodeMin()
2189 GetMasm()->Subs(VixlReg(tmpReg), VixlReg(src0), VixlReg(src1)); in EncodeMax()
2288 GetMasm()->Subs(VixlReg(tmpReg), VixlReg(src1), VixlImm(WORD_SIZE)); in EncodeShl()
2314 GetMasm()->Subs(VixlReg(tmpReg), VixlReg(src1), VixlImm(WORD_SIZE)); in EncodeShr()
2336 GetMasm()->Subs(VixlReg(tmpReg), VixlReg(src1), VixlImm(WORD_SIZE)); in EncodeAShr()
2394 GetMasm()->Subs(VixlReg(dst), VixlReg(src), VixlImm(imm)); in EncodeSub()
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/ |
| H A D | encode.cpp | 1612 GetMasm()->Subs(VixlReg(dst).X(), VixlReg(src0).X(), VixlReg(src1).X()); in EncodeSubOverflow()
1616 GetMasm()->Subs(VixlReg(dst).W(), VixlReg(src0).W(), VixlReg(src1).W()); in EncodeSubOverflow()
1756 GetMasm()->Subs(VixlReg(tmp64), VixlReg(tmp64), VixlShift(Shift(src0.As(INT64_TYPE), extraShift))); in EncodeSignedDiv()
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| /arkcompiler/ets_runtime/ecmascript/compiler/trampoline/aarch64/ |
| H A D | optimized_call.cpp | 245 __ Subs(tmp, expectedNumArgs, actualNumArgs); in OptimizedCallAndPushArgv()
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