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Searched defs:src0_reg (Results 1 - 2 of 2) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_disasm.c54 uint32_t src0_reg : 9; member
/third_party/mesa3d/src/amd/compiler/
H A Daco_lower_to_hw_instr.cpp199 emit_int64_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, in emit_int64_dpp_op() argument
299 emit_int64_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, in emit_int64_op() argument
386 emit_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, ReduceOp op, unsigned size, unsigned dpp_ctrl, unsigned row_mask, unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL) emit_dpp_op() argument
427 emit_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, ReduceOp op, unsigned size) emit_op() argument
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