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/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.h957 void WasmRvvExtractLane(Register dst, VRegister src, int8_t idx, VSew sew, in WasmRvvExtractLane() argument
H A Dassembler-riscv64.h1324 inline int32_t sew() const { return 2 ^ (sew_ + 3); } in sew() function in v8::internal::Assembler::VectorUnit
1336 void set(Register rd, VSew sew, Vlmul lmul) { in set() argument
1345 void set(Register rd, int8_t sew, int8_t lmul) { in set() argument
1360 set(Register rd, Register rs1, VSew sew, Vlmul lmul) set() argument
1369 set(VSew sew, Vlmul lmul) set() argument
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H A Dmacro-assembler-riscv64.cc3923 WasmRvvEq(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvEq() argument
3932 WasmRvvNe(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvNe() argument
3941 WasmRvvGeS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGeS() argument
3950 WasmRvvGeU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGeU() argument
3959 WasmRvvGtS(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGtS() argument
3968 WasmRvvGtU(VRegister dst, VRegister lhs, VRegister rhs, VSew sew, Vlmul lmul) WasmRvvGtU() argument
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/third_party/node/deps/v8/src/diagnostics/riscv64/
H A Ddisasm-riscv64.cc291 const char* sew = instr->RvvSEW(); in PrintRvvSEW() local
/third_party/node/deps/v8/src/compiler/backend/riscv64/
H A Dinstruction-selector-riscv64.cc410 EmitS128Load(InstructionSelector* selector, Node* node, InstructionCode opcode, VSew sew, Vlmul lmul) EmitS128Load() argument

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