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Searched defs:mux_table (Results 1 - 17 of 17) sorted by relevance

/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-gpr-mux.c24 const u32 *mux_table; member
74 imx_clk_gpr_mux(const char *name, const char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask) imx_clk_gpr_mux() argument
/kernel/linux/linux-5.10/drivers/clk/at91/
H A Dclk-programmable.c24 u32 *mux_table; member
189 at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table) at91_clk_register_programmable() argument
H A Dclk-generated.c26 u32 *mux_table; member
288 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) at91_clk_register_generated() argument
H A Dsama7g5.c932 u32 *mux_table; in sama7g5_pmc_setup() local
1018 u32 *mux_table; in sama7g5_pmc_setup() local
[all...]
H A Dclk-master.c40 u32 *mux_table; member
390 at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) at91_clk_sama7g5_register_master() argument
H A Ddt-compat.c679 of_at91_clk_prog_setup(struct device_node *np, const struct clk_programmable_layout *layout, u32 *mux_table) of_at91_clk_prog_setup() argument
/kernel/linux/linux-6.6/drivers/clk/at91/
H A Dclk-generated.c26 u32 *mux_table; member
319 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const struct clk_pcr_layout *layout, const char *name, const char **parent_names, struct clk_hw **parent_hws, u32 *mux_table, u8 num_parents, u8 id, const struct clk_range *range, int chg_pid) at91_clk_register_generated() argument
H A Dclk-programmable.c24 u32 *mux_table; member
216 at91_clk_register_programmable(struct regmap *regmap, const char *name, const char **parent_names, struct clk_hw **parent_hws, u8 num_parents, u8 id, const struct clk_programmable_layout *layout, u32 *mux_table) at91_clk_register_programmable() argument
H A Dsama7g5.c1108 u32 *mux_table; in sama7g5_pmc_setup() local
1204 u32 *mux_table; in sama7g5_pmc_setup() local
[all...]
H A Dclk-master.c34 u32 *mux_table; member
812 at91_clk_sama7g5_register_master(struct regmap *regmap, const char *name, int num_parents, const char **parent_names, struct clk_hw **parent_hws, u32 *mux_table, spinlock_t *lock, u8 id, bool critical, int chg_pid) at91_clk_sama7g5_register_master() argument
H A Ddt-compat.c736 of_at91_clk_prog_setup(struct device_node *np, const struct clk_programmable_layout *layout, u32 *mux_table) of_at91_clk_prog_setup() argument
/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk.h80 u32 *mux_table; member
90 u32 *mux_table; member
/kernel/linux/linux-5.10/drivers/net/ethernet/ti/
H A Dcpts.c660 u32 *mux_table; in cpts_of_mux_clk_setup() local
/kernel/linux/linux-6.6/drivers/clk/mmp/
H A Dclk.h80 u32 *mux_table; member
90 u32 *mux_table; member
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk.c38 rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_branch() argument
H A Dclk.h538 u32 *mux_table; member
/kernel/linux/linux-6.6/drivers/net/ethernet/ti/
H A Dcpts.c648 u32 *mux_table; in cpts_of_mux_clk_setup() local

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