Searched defs:is_mec (Results 1 - 2 of 2) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | si_cmd_buffer.c | 927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, in si_cs_emit_write_event_eop() argument
1029 si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) in si_emit_acquire_mem() argument
1051 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) gfx10_cs_emit_cache_flush() argument
1232 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) si_cs_emit_cache_flush() argument
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| H A D | radv_device.c | 4597 const bool is_mec = queue->qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7; in radv_update_preamble_cs() local
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