i0 (definition) in projects: kernel - OpenGrok search results

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Searched defs:i0 (Results 1 - 25 of 43) sorted by relevance

/kernel/linux/linux-5.10/tools/testing/selftests/proc/
H A D	proc-uptime-001.c	`28 uint64_t start, u0, u1, i0, i1; in main() local`
H A D	proc-uptime-002.c	`48 uint64_t u0, u1, i0, i1; in main() local`
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
H A D	mmss_cc.xml.h	64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK() argument 66 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_CC() argument 83 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_MD() argument 97 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_NS() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
H A D	mmss_cc.xml.h	71 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK() argument 73 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_CC() argument 90 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_MD() argument 104 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_NS() argument
H A D	dsi_phy_20nm.xml.h	56 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40i0; } in REG_DSI_20nm_PHY_LN() argument 58 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40i0; } in REG_DSI_20nm_PHY_LN_CFG_0() argument 60 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40i0; } in REG_DSI_20nm_PHY_LN_CFG_1() argument 62 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40i0; } in REG_DSI_20nm_PHY_LN_CFG_2() argument 64 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_3() argument 66 REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_4() argument 68 REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_DATAPATH() argument 70 REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) REG_DSI_20nm_PHY_LN_DEBUG_SEL() argument 72 REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_STR_0() argument 74 REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_STR_1() argument [all...]
H A D	dsi_phy_10nm.xml.h	126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80i0; } in REG_DSI_10nm_PHY_LN() argument 128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80i0; } in REG_DSI_10nm_PHY_LN_CFG0() argument 130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80i0; } in REG_DSI_10nm_PHY_LN_CFG1() argument 132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80i0; } in REG_DSI_10nm_PHY_LN_CFG2() argument 134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG3() argument 136 REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_10nm_PHY_LN_TEST_DATAPATH() argument 138 REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) REG_DSI_10nm_PHY_LN_PIN_SWAP() argument 140 REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL() argument 142 REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL() argument 144 REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL() argument 146 REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL() argument 148 REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_LPRX_CTRL() argument 150 REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_TX_DCTRL() argument [all...]
H A D	dsi_phy_14nm.xml.h	117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80i0; } in REG_DSI_14nm_PHY_LN() argument 119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80i0; } in REG_DSI_14nm_PHY_LN_CFG0() argument 127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80i0; } in REG_DSI_14nm_PHY_LN_CFG1() argument 130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80i0; } in REG_DSI_14nm_PHY_LN_CFG2() argument 132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG3() argument 134 REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_14nm_PHY_LN_TEST_DATAPATH() argument 136 REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) REG_DSI_14nm_PHY_LN_TEST_STR() argument 138 REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_4() argument 146 REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_5() argument 154 REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_6() argument 162 REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_7() argument 170 REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_8() argument 178 REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_9() argument 192 REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_10() argument 200 REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_11() argument 208 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0() argument 210 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1() argument 212 REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) REG_DSI_14nm_PHY_LN_VREG_CNTRL() argument [all...]
H A D	dsi_phy_28nm_8960.xml.h	56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40i0; } in REG_DSI_28nm_8960_PHY_LN() argument 58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument 60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument 62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2() argument 64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument 66 REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument 68 REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument [all...]
H A D	dsi_phy_7nm.xml.h	160 static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80i0; } in REG_DSI_7nm_PHY_LN() argument 162 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80i0; } in REG_DSI_7nm_PHY_LN_CFG0() argument 164 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80i0; } in REG_DSI_7nm_PHY_LN_CFG1() argument 166 static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80i0; } in REG_DSI_7nm_PHY_LN_CFG2() argument 168 static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_7nm_PHY_LN_TEST_DATAPATH() argument 170 REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) REG_DSI_7nm_PHY_LN_PIN_SWAP() argument 172 REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) REG_DSI_7nm_PHY_LN_LPRX_CTRL() argument 174 REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) REG_DSI_7nm_PHY_LN_TX_DCTRL() argument [all...]
H A D	dsi_phy_28nm.xml.h	56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40i0; } in REG_DSI_28nm_PHY_LN() argument 58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40i0; } in REG_DSI_28nm_PHY_LN_CFG_0() argument 60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40i0; } in REG_DSI_28nm_PHY_LN_CFG_1() argument 62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40i0; } in REG_DSI_28nm_PHY_LN_CFG_2() argument 64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3() argument 66 REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_4() argument 68 REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_DATAPATH() argument 70 REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) REG_DSI_28nm_PHY_LN_DEBUG_SEL() argument 72 REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_STR_0() argument 74 REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_STR_1() argument [all...]
H A D	dsi.xml.h	`448 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4i0; } in REG_DSI_RDBK() argument 450 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4i0; } in REG_DSI_RDBK_DATA() argument`
/kernel/linux/linux-5.10/fs/jffs2/
H A D	compr_rubin.c	`105 long i0, i1; in encode() local 203 long i0, threshol in decode() local [all...]`
/kernel/linux/linux-6.6/fs/jffs2/
H A D	compr_rubin.c	`105 long i0, i1; in encode() local 203 long i0, threshol in decode() local [all...]`
/kernel/linux/linux-5.10/arch/powerpc/sysdev/xive/
H A D	common.c	`230 u32 i0, i1, idx; in xive_dump_eq() local 1594 u32 i0, i1, idx; in xive_debug_show_cpu() local`
/kernel/linux/linux-5.10/arch/powerpc/kvm/
H A D	book3s_xive.c	`2123 u32 i0, i1, idx; in kvmppc_xive_debug_show_queues() local`
/kernel/linux/linux-6.6/arch/powerpc/kvm/
H A D	book3s_xive.c	`2817 u32 i0, i1, idx; in kvmppc_xive_debug_show_queues() local`
/kernel/linux/linux-5.10/sound/pci/cs46xx/
H A D	cs46xx_dsp_scb_types.h	`1110 u32 i0; member`
/kernel/linux/linux-6.6/sound/pci/cs46xx/
H A D	cs46xx_dsp_scb_types.h	`1110 u32 i0; member`
/kernel/linux/linux-6.6/arch/powerpc/sysdev/xive/
H A D	common.c	`258 u32 i0, i1, idx; in xive_dump_eq() local`
/kernel/linux/linux-5.10/fs/jfs/
H A D	jfs_dmap.c	`3427 int i, i0 = true, j, j0 = true, k, n; in dbExtendFS() local`
/kernel/linux/linux-5.10/lib/crypto/
H A D	curve25519-hacl64.c	`195 u64 i0; in fmul_fmul() local 253 u64 i0; in fsquare_fsquare_() local 609 u64 i0, i1, i2, i3, i4, output0, output1, output2, output3, output4; in format_fexpand() local 679 u64 i0; format_fcontract_second_carry_full() local [all...]`
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/edp/
H A D	edp.xml.h	`276 static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40i0; } in REG_EDP_PHY_LN() argument 278 static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40i0; } in REG_EDP_PHY_LN_PD_CTL() argument`
/kernel/linux/linux-6.6/fs/jfs/
H A D	jfs_dmap.c	`3363 int i, i0 = true, j, j0 = true, k, n; in dbExtendFS() local`
/kernel/linux/linux-6.6/lib/crypto/
H A D	curve25519-hacl64.c	`193 u64 i0; in fmul_fmul() local 251 u64 i0; in fsquare_fsquare_() local 607 u64 i0, i1, i2, i3, i4, output0, output1, output2, output3, output4; in format_fexpand() local 677 u64 i0; format_fcontract_second_carry_full() local [all...]`
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
H A D	mdp4.xml.h	319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument 321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument 323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument 337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument 339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument 341 REG_MDP4_OVLP_OPMODE(uint32_t i0) REG_MDP4_OVLP_OPMODE() argument 353 REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE() argument 355 REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_OP() argument 375 REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_FG_ALPHA() argument 377 REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_BG_ALPHA() argument 379 REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument 381 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument 383 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument 385 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument 397 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3() argument 399 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3_SEL() argument 402 REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) REG_MDP4_OVLP_TRANSP_LOW0() argument 404 REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) REG_MDP4_OVLP_TRANSP_LOW1() argument 406 REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) REG_MDP4_OVLP_TRANSP_HIGH0() argument 408 REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) REG_MDP4_OVLP_TRANSP_HIGH1() argument 410 REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) REG_MDP4_OVLP_CSC_CONFIG() argument 412 REG_MDP4_OVLP_CSC(uint32_t i0) REG_MDP4_OVLP_CSC() argument 415 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV() argument 417 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV_VAL() argument 419 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV() argument 421 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument 423 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV() argument 425 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV_VAL() argument 427 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV() argument 429 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument 431 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV() argument 433 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV_VAL() argument 437 REG_MDP4_LUTN(uint32_t i0) REG_MDP4_LUTN() argument 439 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT() argument 441 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT_VAL() argument 445 REG_MDP4_DMA_E_QUANT(uint32_t i0) REG_MDP4_DMA_E_QUANT() argument 456 REG_MDP4_DMA(enum mdp4_dma i0) REG_MDP4_DMA() argument 458 REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_CONFIG() argument 487 REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_SIZE() argument 501 REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_BASE() argument 503 REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_STRIDE() argument 505 REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_DST_SIZE() argument 519 REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_SIZE() argument 533 REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BASE() argument 535 REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_POS() argument 549 REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BLEND_CONFIG() argument 559 REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BLEND_PARAM() argument 561 REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) REG_MDP4_DMA_BLEND_TRANS_LOW() argument 563 REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) REG_MDP4_DMA_BLEND_TRANS_HIGH() argument 565 REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_FETCH_CONFIG() argument 567 REG_MDP4_DMA_CSC(enum mdp4_dma i0) REG_MDP4_DMA_CSC() argument 570 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV() argument 572 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV_VAL() argument 574 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV() argument 576 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV_VAL() argument 578 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV() argument 580 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV_VAL() argument 582 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV() argument 584 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV_VAL() argument 586 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV() argument 588 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV_VAL() argument 590 REG_MDP4_PIPE(enum mdp4_pipe i0) REG_MDP4_PIPE() argument 592 REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_SIZE() argument 606 REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_XY() argument 620 REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_DST_SIZE() argument 634 REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) REG_MDP4_PIPE_DST_XY() argument 648 REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP0_BASE() argument 650 REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP1_BASE() argument 652 REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP2_BASE() argument 654 REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP3_BASE() argument 656 REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_STRIDE_A() argument 670 REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_STRIDE_B() argument 684 REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_SSTILE_FRAME_SIZE() argument 698 REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_FORMAT() argument 759 REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_UNPACK() argument 785 REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) REG_MDP4_PIPE_OP_MODE() argument 810 REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) REG_MDP4_PIPE_PHASEX_STEP() argument 812 REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) REG_MDP4_PIPE_PHASEY_STEP() argument 814 REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) REG_MDP4_PIPE_FETCH_CONFIG() argument 816 REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) REG_MDP4_PIPE_SOLID_COLOR() argument 818 REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) REG_MDP4_PIPE_CSC() argument 821 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV() argument 823 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV_VAL() argument 825 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV() argument 827 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument 829 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV() argument 831 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV_VAL() argument 833 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV() argument 835 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument 837 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV() argument 839 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV_VAL() argument 938 REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL() argument 940 REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0() argument 966 REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4() argument [all...]

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