| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v2_4.c | 382 u32 f32_cntl; in sdma_v2_4_enable() local
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| H A D | cik_sdma.c | 347 u32 f32_cntl, phase_quantum = 0; in cik_ctx_switch_enable() local
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| H A D | sdma_v5_2.c | 503 u32 f32_cntl, phase_quantum = 0; in sdma_v5_2_ctx_switch_enable() local
542 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable() local
557 u32 f32_cntl; in sdma_v5_2_enable() local
568 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable() local
[all...] |
| H A D | sdma_v5_0.c | 565 u32 f32_cntl = 0, phase_quantum = 0; in sdma_v5_0_ctx_switch_enable() local
608 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable() local
623 u32 f32_cntl; in sdma_v5_0_enable() local
637 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable() local
[all...] |
| H A D | sdma_v3_0.c | 556 u32 f32_cntl, phase_quantum = 0; in sdma_v3_0_ctx_switch_enable() local
617 u32 f32_cntl; sdma_v3_0_enable() local
[all...] |
| H A D | sdma_v4_0.c | 1036 u32 f32_cntl, phase_quantum = 0; in sdma_v4_0_ctx_switch_enable() local
1096 u32 f32_cntl; in sdma_v4_0_enable() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v2_4.c | 376 u32 f32_cntl; in sdma_v2_4_enable() local
|
| H A D | cik_sdma.c | 343 u32 f32_cntl, phase_quantum = 0; in cik_ctx_switch_enable() local
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| H A D | sdma_v3_0.c | 550 u32 f32_cntl, phase_quantum = 0; in sdma_v3_0_ctx_switch_enable() local
611 u32 f32_cntl; sdma_v3_0_enable() local
[all...] |
| H A D | sdma_v5_0.c | 596 u32 f32_cntl = 0, phase_quantum = 0; in sdma_v5_0_ctx_switch_enable() local
639 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable() local
654 u32 f32_cntl; in sdma_v5_0_enable() local
668 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable() local
[all...] |
| H A D | sdma_v5_2.c | 401 u32 f32_cntl, phase_quantum = 0; in sdma_v5_2_ctx_switch_enable() local
442 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable() local
458 u32 f32_cntl; in sdma_v5_2_enable() local
470 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable() local
[all...] |
| H A D | sdma_v6_0.c | 418 u32 f32_cntl; in sdma_v6_0_ctxempty_int_enable() local
426 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); in sdma_v6_0_ctxempty_int_enable() local
441 u32 f32_cntl; in sdma_v6_0_enable() local
[all...] |
| H A D | sdma_v4_0.c | 938 u32 f32_cntl, phase_quantum = 0; in sdma_v4_0_ctx_switch_enable() local
1000 u32 f32_cntl; in sdma_v4_0_enable() local
[all...] |
| H A D | sdma_v4_4_2.c | 511 u32 f32_cntl, phase_quantum = 0; in sdma_v4_4_2_inst_ctx_switch_enable() local
566 u32 f32_cntl; in sdma_v4_4_2_inst_enable() local
[all...] |