H A D | df_v3_6.c | 346 df_v3_6_pmc_has_counter(struct amdgpu_device *adev, uint64_t config, int counter_idx) df_v3_6_pmc_has_counter() argument 357 df_v3_6_pmc_get_addr(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_ctrl, uint32_t *lo_base_addr, uint32_t *hi_base_addr) df_v3_6_pmc_get_addr() argument 391 df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint32_t *lo_base_addr, uint32_t *hi_base_addr) df_v3_6_pmc_get_read_settings() argument 402 df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint32_t *lo_base_addr, uint32_t *hi_base_addr, uint32_t *lo_val, uint32_t *hi_val, bool is_enable) df_v3_6_pmc_get_ctrl_settings() argument 460 df_v3_6_pmc_set_deferred(struct amdgpu_device *adev, uint64_t config, int counter_idx, bool is_deferred) df_v3_6_pmc_set_deferred() argument 478 df_v3_6_pmc_is_deferred(struct amdgpu_device *adev, uint64_t config, int counter_idx) df_v3_6_pmc_is_deferred() argument 489 df_v3_6_pmc_release_cntr(struct amdgpu_device *adev, uint64_t config, int counter_idx) df_v3_6_pmc_release_cntr() argument 498 df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev, uint64_t config, int counter_idx) df_v3_6_reset_perfmon_cntr() argument 514 df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_add) df_v3_6_pmc_start() argument 556 df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, int counter_idx, int is_remove) df_v3_6_pmc_stop() argument 593 df_v3_6_pmc_get_count(struct amdgpu_device *adev, uint64_t config, int counter_idx, uint64_t *count) df_v3_6_pmc_get_count() argument [all...] |