| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/x64/ |
| H A D | macro_assembler_x64.cpp | 24 x64::Register baseReg = (dstStackSlot.IsFrameBase()) ? x64::rbp : x64::rsp; in Move() local
43 x64::Register baseReg = (stackSlot.IsFrameBase()) ? x64::rbp : x64::rsp; in Cmp() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/ |
| H A D | macro_assembler.h | 41 StackSlotOperand(BaseRegister baseReg, int32_t stackOffset) in StackSlotOperand() argument
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/ |
| H A D | operand.cpp | 166 RegOperand *baseReg = GetBaseRegister(); in Less() local
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| H A D | reg_alloc_lsra.cpp | 1007 uint32 baseReg = isInt ? firstIntReg : firstFpReg; in UpdateParamAllocateInfo() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/aarch64/ |
| H A D | aarch64_insn.cpp | 130 auto *baseReg = v->GetBaseRegister(); in Visit() local
187 auto *baseReg = v->GetBaseRegister(); in Visit() local
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| H A D | aarch64_cgfunc.cpp | 571 MemOperand &AArch64CGFunc::CreateReplacementMemOperand(uint32 bitLen, RegOperand &baseReg, int64 offset) in CreateReplacementMemOperand() argument
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| /arkcompiler/ets_runtime/ecmascript/compiler/codegen/maple/maple_be/src/cg/x86_64/ |
| H A D | x64_proepilog.cpp | 39 RegOperand &baseReg = cgFunc.GetOpndBuilder()->CreatePReg(x64::RBP, k64BitSize, kRegTyInt); in GenerateCalleeSavedRegs() local
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| H A D | x64_MPIsel.cpp | 432 RegOperand &baseReg = cgFunc->GetOpndBuilder()->CreatePReg(x64::RBP, GetPrimTypeBitSize(PTY_i64), kRegTyInt); in SelectRangeGoto() local
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| /arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/ |
| H A D | macro_assembler_aarch64.cpp | 38 aarch64::Register baseReg = (dstStackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in Move() local
60 aarch64::Register baseReg = (stackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in Cmp() local
106 aarch64::Register baseReg = (dstStackSlot.IsFrameBase()) ? aarch64::Register(aarch64::FP) : in SaveReturnRegister() local
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| /arkcompiler/ets_frontend/es2panda/ir/base/ |
| H A D | classDefinition.cpp | 111 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
393 compiler::VReg baseReg = CompileHeritageClause(pg); in Compile() local
685 compiler::VReg baseReg = CompileHeritageClause(pg); in CompileSendableClass() local
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| /arkcompiler/ets_frontend/ets2panda/compiler/core/ |
| H A D | JSCompiler.cpp | 51 compiler::VReg baseReg = pg->AllocReg(); in CompileHeritageClause() local
382 compiler::VReg baseReg = CompileHeritageClause(pg, node); in Compile() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/amd64/ |
| H A D | encode.cpp | 3118 auto baseReg = ArchReg(base); in LoadStoreRegisters() local
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch32/ |
| H A D | encode.cpp | 234 auto baseReg = VixlReg(mem.GetBase()); in ConvertMem() local
849 auto baseReg = VixlReg(mem.GetBase()); in PrepareMemLdS() local
922 auto baseReg = VixlReg(mem.GetBase()); PrepareMemLdSForFloat() local
3168 vixl::aarch32::Register baseReg = VixlReg(base); LoadStoreRegistersMainLoop() local
3195 vixl::aarch32::Register baseReg = VixlReg(base); LoadStoreRegisters() local
3225 ConstructAddForBigOffset(vixl::aarch32::Register tmp, vixl::aarch32::Register *baseReg, ssize_t *slot, ssize_t maxOffset, bool isFp) ConstructAddForBigOffset() argument
3255 vixl::aarch32::Register baseReg = vixl::aarch32::sp; LoadStoreRegisters() local
[all...] |
| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/ |
| H A D | codegen.cpp | 2810 void PostWriteBarrier::EncodeCalculateCardIndex(Reg baseReg, ScopedTmpReg *tmp, ScopedTmpReg *tmp1) in EncodeCalculateCardIndex() argument
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| /arkcompiler/runtime_core/static_core/compiler/optimizer/code_generator/target/aarch64/ |
| H A D | encode.cpp | 142 auto baseReg = Reg(mem.GetBase().GetId(), INT64_TYPE); in ConvertMem() local
2036 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdr() local
2094 [[maybe_unused]] auto baseReg = mem.GetBase(); in EncodeLdrAcquireInvalid() local
2172 auto baseReg = mem.GetBase(); CheckAlignment() local
3085 auto baseReg = VixlReg(base); LoadStorePair() local
3097 auto baseReg = VixlReg(base); LoadStoreReg() local
3185 LoadStoreRegistersLoop(RegMask registers, ssize_t slot, size_t startReg, bool isFp, const vixl::aarch64::Register &baseReg) LoadStoreRegistersLoop() argument
[all...] |
| /arkcompiler/runtime_core/static_core/libllvmbackend/lowering/ |
| H A D | llvm_ir_constructor.cpp | 1466 std::string baseReg = representable ? "sp" : "x16"; in CreateInterpreterReturnRestoreRegs() local
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