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Searched defs:anv_batch_emit (Results 1 - 5 of 5) sorted by relevance

/third_party/mesa3d/src/intel/vulkan/
H A DgenX_gpu_memcpy.c59 anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_common_so_memcpy() function
74 anv_batch_emit(batch, GENX(3DSTATE_SBE), sbe) { in emit_common_so_memcpy() function
104 anv_batch_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) { emit_common_so_memcpy() function
109 anv_batch_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf) { emit_common_so_memcpy() function
165 anv_batch_emit(batch, GENX(3DSTATE_SO_BUFFER), sob) { emit_so_memcpy() function
196 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), load) { emit_so_memcpy() function
214 anv_batch_emit(batch, GENX(3DSTATE_STREAMOUT), so) { emit_so_memcpy() function
226 anv_batch_emit(batch, GENX(3DPRIMITIVE), prim) { emit_so_memcpy() function
250 anv_batch_emit(batch, GENX(PIPELINE_SELECT), ps) { emit_so_memcpy_init() function
[all...]
H A DgenX_state.c66 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) { in emit_slice_hashing_state() function
71 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) { in emit_slice_hashing_state() function
183 anv_batch_emit(batch, GENX(STATE_BASE_ADDRESS), sba) { in init_common_queue_state() function
724 anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { emit_multisample() function
767 anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) { emit_sample_pattern() function
842 anv_batch_emit(batch, GENX(3DSTATE_CPS), cps) { emit_shading_rate() function
860 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { emit_shading_rate() function
868 anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) { emit_shading_rate() function
[all...]
H A DgenX_pipeline.c297 anv_batch_emit(batch, GFX7_PIPE_CONTROL, pc) { in emit_urb_setup() function
305 anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) { in emit_urb_setup() function
[all...]
H A DgenX_cmd_buffer.c2096 anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) { emit_apply_pipe_flushes() function
2241 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { emit_apply_pipe_flushes() function
2265 anv_batch_emit(batch, GENX(PIPE_CONTROL), pipe) { emit_apply_pipe_flushes() function
2312 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { emit_apply_pipe_flushes() function
5542 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { CmdDispatchIndirect() function
5550 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { CmdDispatchIndirect() function
5558 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { CmdDispatchIndirect() function
5565 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { CmdDispatchIndirect() function
5576 anv_batch_emit(batch, GENX(MI_PREDICATE), mip) { CmdDispatchIndirect() function
7504 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { cmd_emit_timestamp() function
[all...]
H A Danv_private.h1686 #define anv_batch_emit(batch, cmd, name) \ macro

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