VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 (definition) in projects: kernel - OpenGrok search results

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Searched defs:VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 (Results 1 - 2 of 2) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
H A D	sil-sii8620.h	`757 #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30 macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
H A D	sil-sii8620.h	`757 #define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30 macro`

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