/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
H A D | RISCVMergeBaseOffset.cpp | 139 Register Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local [all...] |
/third_party/mesa3d/src/asahi/compiler/ |
H A D | agx_pack.c | 506 bool Rt, At, Ot; in agx_pack_instr() local 550 bool Rt, Ot, Ct, St; in agx_pack_instr() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 374 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local 385 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local 397 MCOperand &Rt = Inst.getOperand(2); HexagonProcessInstruction() local 594 MCOperand &Rt = Inst.getOperand(1); HexagonProcessInstruction() local [all...] |
H A D | HexagonSplitDouble.cpp | 376 Register Rt = MI->getOperand(2).getReg(); in profit() local
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H A D | HexagonInstrInfo.cpp | 1237 Register Rt = Op3.getReg(); in expandPostRAPseudo() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore() local
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H A D | ARMBaseInstrInfo.cpp | 3374 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3381 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3411 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3423 Register Rt = MI.getOperand(0).getReg(); in getNumMicroOpsSwiftLdSt() local 3461 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local 3487 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local 3497 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local 3534 Register Rt = MI.getOperand(0).getReg(); getNumMicroOpsSwiftLdSt() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 1031 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local 1092 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeSignedLdStInstruction() local 1290 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodeExclusiveLdStInstruction() local 1373 unsigned Rt = fieldFromInstruction(insn, 0, 5); DecodePairLdStInstruction() local 1753 uint64_t Rt = fieldFromInstruction(insn, 0, 5); DecodeTestAndBranch() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 676 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local 704 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local 749 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeDaddiGroupBranch() local 777 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodePOP37GroupBranchMMR6() local 818 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodePOP65GroupBranchMMR6() local 857 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodePOP75GroupBranchMMR6() local 901 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBlezlGroupBranch() local 946 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBgtzlGroupBranch() local 988 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBgtzGroupBranch() local 1037 InsnType Rt = fieldFromInstruction(insn, 16, 5); DecodeBlezGroupBranch() local 1093 InsnType Rt = fieldFromInstruction(Insn, 16, 5); DecodeDEXT() local 1135 InsnType Rt = fieldFromInstruction(Insn, 16, 5); DecodeDINS() local 1153 InsnType Rt = fieldFromInstruction(Insn, 16, 5); DecodeCRC() local 2050 unsigned Rt = fieldFromInstruction(Insn, 16, 5); DecodeSpecial3LlSc() local 2560 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodeBgtzGroupBranchMMR6() local 2609 InsnType Rt = fieldFromInstruction(insn, 21, 5); DecodeBlezGroupBranchMMR6() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
H A D | IceAssemblerMIPS32.cpp | 210 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRsRt() local 221 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16() local 236 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); in emitRtRsImm16Rel() local 272 const IValueT Rt in emitRdRtSa() local 286 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); emitRdRsRt() local 346 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); emitCOP1FmtRtFsFd() local 359 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InsnName); emitCOP1MovRtFs() local 668 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "lui"); lui() local 687 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "ldc1"); ldc1() local 749 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "lwc1"); lwc1() local 823 const IValueT Rt = 0; // $0 move() local 1075 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "sdc1"); sdc1() local 1131 const IValueT Rt = encodeFPRegister(OpRt, "Ft", "swc1"); swc1() local 1158 const IValueT Rt = encodeGPRegister(OpRt, "Rt", "teq"); teq() local 1237 IValueT Rt = encodeGPRegister(OpRt, "Rt", "branch"); emitBr() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1361 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local 1800 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local 1820 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local 1843 MCOperand &Rt = Inst.getOperand(2); processInstruction() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3516 Register Rt = MI.getOperand(1).getReg(); in emitST_F16_PSEUDO() local 3581 Register Rt = RegInfo.createVirtualRegister(RC); in emitLD_F16_PSEUDO() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1828 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local 1976 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local 3767 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadShift() local 3851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadImm8() local 3935 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadImm12() local 4015 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadT() local 4053 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LoadLabel() local 4290 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LdStPre() local 4751 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeDoubleRegLoad() local 4774 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeDoubleRegStore() local 4799 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeLDRPreImm() local 4824 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeLDRPreReg() local 4851 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSTRPreImm() local 4876 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSTRPreReg() local 5447 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeVMOVSRR() local 5473 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeVMOVRRS() local 5530 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2LDRDPreInstruction() local 5567 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeT2STRDPreInstruction() local 5636 unsigned Rt = fieldFromInstruction(Insn, 12, 4); DecodeSwap() local 5817 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecodeLDR() local 5846 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecoderForMRRC2AndMCRR2() local 5903 unsigned Rt = fieldFromInstruction(Val, 12, 4); DecodeForVMRSandVMSR() local 6422 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeMVEVMOVQtoDReg() local 6445 unsigned Rt = fieldFromInstruction(Insn, 0, 4); DecodeMVEVMOVDRegtoQ() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 3973 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 3990 unsigned Rt = Inst.getOperand(0).getReg(); in validateInstruction() local 4003 unsigned Rt = Inst.getOperand(1).getReg(); in validateInstruction() local 4019 unsigned Rt in validateInstruction() local 4052 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local 4071 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local 4087 unsigned Rt = Inst.getOperand(1).getReg(); validateInstruction() local [all...] |
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 7134 unsigned Rt = MRI->getEncodingValue(Reg1); in ParseInstruction() local 7255 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(RtIndex).getReg()); in validateLDRDSTRD() local 7480 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg()); validateInstruction() local 7513 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); validateInstruction() local [all...] |