| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| H A D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode() argument
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonAsmPrinter.cpp | 409 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
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| H A D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; in isInduction() local
375 Register Rs = MI->getOperand(1).getReg(); in profit() local
476 collectIndRegsForLoop(const MachineLoop *L, USet &Rs) collectIndRegsForLoop() argument
584 USet Rs; collectIndRegs() local
[all...] |
| H A D | HexagonConstExtenders.cpp | 293 Register Rs; member
446 HCE::Register Rs; global() member
1504 Register Rs = ExtI.second.Rs; // Only one reg allowed now. calculatePlacement() local
1783 Register Rs = MI.getOperand(IsSub ? 3 : 2); replaceInstrExpr() local
[all...] |
| H A D | HexagonFrameLowering.cpp | 2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
[all...] |
| H A D | HexagonInstrInfo.cpp | 1236 Register Rs = Op2.getReg(); in expandPostRAPseudo() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1293 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP35GroupBranchMMR6() local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeDaddiGroupBranch() local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP37GroupBranchMMR6() local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP65GroupBranchMMR6() local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodePOP75GroupBranchMMR6() local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBlezlGroupBranch() local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBgtzlGroupBranch() local
987 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBgtzGroupBranch() local
1036 InsnType Rs = fieldFromInstruction(insn, 21, 5); DecodeBlezGroupBranch() local
1092 InsnType Rs = fieldFromInstruction(Insn, 21, 5); DecodeDEXT() local
1134 InsnType Rs = fieldFromInstruction(Insn, 21, 5); DecodeDINS() local
1152 InsnType Rs = fieldFromInstruction(Insn, 21, 5); DecodeCRC() local
2561 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodeBgtzGroupBranchMMR6() local
2610 InsnType Rs = fieldFromInstruction(insn, 16, 5); DecodeBlezGroupBranchMMR6() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 997 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
259 const IValueT Rs in emitFtRsImm16() local
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); emitRdRsRt() local
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); clz() local
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); jalr() local
822 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); move() local
841 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); movf() local
876 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); movt() local
914 IValueT Rs = encodeGPRegister(OpRs, "Rs", "mthi"); mthi() local
921 IValueT Rs = encodeGPRegister(OpRs, "Rs", "mtlo"); mtlo() local
1157 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "teq"); teq() local
1232 IValueT Rs = encodeGPRegister(OpRs, "Rs", "branch"); emitBr() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1618 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1638 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1658 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1681 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1714 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1724 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1766 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1783 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
1912 MCOperand &Rs = Inst.getOperand(1); processInstruction() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3528 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1492 unsigned Rs = fieldFromInstruction(Val, 8, 4); in DecodeSORegRegOperand() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4086 unsigned Rs = Inst.getOperand(0).getReg(); in validateInstruction() local
4099 unsigned Rs = Inst.getOperand(0).getReg(); in validateInstruction() local
|