| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 75 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const MCPhysReg (&Regs)[N]) decodeRegisterClass() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 82 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size) decodeRegisterClass() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 83 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) GetGroupRegs() argument
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| H A D | CallingConvLower.cpp | 199 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType() argument
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| H A D | MachineCopyPropagation.cpp | 99 void markRegsUnavailable(ArrayRef<unsigned> Regs, in markRegsUnavailable() argument
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| H A D | LiveDebugValues.cpp | 1440 static void collectRegDefs(const MachineInstr &MI, DefinedRegsSet &Regs, in collectRegDefs() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 135 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 47 SmallVector<Register, 4> Regs; member
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| H A D | LegalizationArtifactCombiner.h | 364 SmallVector<Register, 2> Regs; in tryCombineMerges() local
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| H A D | IRTranslator.h | 566 auto Regs = getOrCreateVRegs(Val); in getOrCreateVReg() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/ |
| H A D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent() argument
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 344 auto Regs = RC.getRegisters(); in allocateVGPRSpillToAGPR() local
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| H A D | AMDGPUCallLowering.cpp | 489 packSplitRegsToOrigType(MachineIRBuilder &B, ArrayRef<Register> OrigRegs, ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT) packSplitRegsToOrigType() argument
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| H A D | SILoadStoreOptimizer.cpp | 520 const unsigned Regs = getRegs(I->getOpcode(), TII); in setMI() local
1236 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1298 const unsigned Regs in mergeTBufferLoadPair() local
1377 const unsigned Regs = getRegs(Opcode, *TII); mergeTBufferStorePair() local
1539 const unsigned Regs = getRegs(Opcode, *TII); mergeBufferStorePair() local
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| H A D | SIMachineScheduler.cpp | 1682 void SIScheduleBlockScheduler::addLiveRegs(std::set<unsigned> &Regs) { in addLiveRegs() argument
1692 decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs) decreaseLiveRegs() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUPALMetadata.cpp | 161 auto Regs = getRegisters(); in getRegister() local
555 auto Regs = getRegisters(); in toString() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 388 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); in determineCalleeSaves() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 850 SmallVector<unsigned, 4> Regs; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigne argument
412 AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) AllocateReg() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 612 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, in ContainsReg() argument
623 CreateLoadStoreMulti( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) CreateLoadStoreMulti() argument
830 CreateLoadStoreDouble( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, ArrayRef<std::pair<unsigned, bool>> Regs, ArrayRef<MachineInstr*> Instrs) const CreateLoadStoreDouble() argument
860 SmallVector<std::pair<unsigned, bool>, 8> Regs; MergeOpsUpdate() local
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| H A D | ARMFrameLowering.cpp | 1074 SmallVector<unsigned, 4> Regs; emitPopInst() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 2454 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; in DecodeRegListOperand16() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 741 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) parseRegister() argument
758 parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) parseRegister() argument
896 parseAddress(OperandVector &Operands, MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind) parseAddress() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 701 SDValue Regs[2]; in selectBDVAddr12Only() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 164 auto *Regs = VMap.getVRegs(Val); in allocateVRegs() local
1032 auto &Regs = *VMap.getVRegs(U); translateBitCast() local
1879 auto &Regs = *VMap.getVRegs(U); translateInsertElement() local
1903 auto &Regs = *VMap.getVRegs(U); translateExtractElement() local
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