| /third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/simd/ |
| H A D | integer.h | 17 glm_uvec4 Reg2; in glm_i128_interleave() local
71 glm_uvec4 Reg2; glm_i128_interleave2() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 94 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
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| H A D | TargetInstrInfo.cpp | 176 Register Reg2 = MI.getOperand(Idx2).getReg(); in commuteInstructionImpl() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
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| H A D | PPCVSXSwapRemoval.cpp | 873 Register Reg2 = MI->getOperand(2).getReg(); in handleSpecialSwappables() local
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| H A D | PPCInstrInfo.cpp | 397 Register Reg2 = MI.getOperand(2).getReg(); in commuteInstructionImpl() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 164 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) addRegReg() argument
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| H A D | X86InstrInfo.cpp | 4945 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg(); in foldMemoryOperandImpl() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 640 unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true); variable
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 447 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) createRegSequence() argument
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| H A D | Thumb2SizeReduction.cpp | 750 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
785 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
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| H A D | ARMFastISel.cpp | 2797 unsigned Reg2 = 0; in SelectShift() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
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| H A D | MipsAsmPrinter.cpp | 874 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) EmitInstrRegReg() argument
894 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) EmitInstrRegRegReg() argument
905 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) EmitMovFPIntPair() argument
[all...] |
| H A D | MipsISelLowering.cpp | 2949 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 783 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, unsigned VM, bool Compr, unsigned Enabled, bool Done) buildEXP() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| H A D | MCDwarf.cpp | 1336 unsigned Reg2 = Instr.getRegister2(); in EmitCFIInstruction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 1867 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing() argument
1890 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing() argument
1907 unsigned Reg2 = AArch64::NoRegister; member
2132 unsigned Reg2 = RPI.Reg2; spillCalleeSavedRegisters() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsTargetStreamer.cpp | 217 emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRR() argument
223 emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2, MCOperand Op3, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRRX() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 900 Register Reg1, Reg2; in parseAddress() local
835 parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2, Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length) parseAddress() argument
1214 Register Reg1, Reg2; parseOperand() local
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2603 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg(); in evaluateHexCompare2() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 7133 unsigned Reg2 = Op2.getReg(); in ParseInstruction() local
|