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Searched defs:Reg1 (Results 1 - 25 of 35) sorted by relevance

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/third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/simd/
H A Dinteger.h16 glm_uvec4 Reg1; in glm_i128_interleave() local
70 glm_uvec4 Reg1; glm_i128_interleave2() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp94 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) { in UnionGroups() argument
H A DTargetInstrInfo.cpp175 Register Reg1 = MI.getOperand(Idx1).getReg(); in commuteInstructionImpl() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstrBuilder.h164 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) addRegReg() argument
H A DX86AvoidStoreForwardingBlocks.cpp395 Register Reg1 = MRI->createVirtualRegister( in buildCopy() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h98 bool contains(unsigned Reg1, unsigned Reg2) const { in contains() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp633 unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true); variable
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp447 createRegSequence( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned Reg1, unsigned Reg2) createRegSequence() argument
H A DThumb2SizeReduction.cpp747 Register Reg1 = MI->getOperand(1).getReg(); in ReduceTo2Addr() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp275 adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const adjustStackPtrBig() argument
H A DMicroMipsSizeReduction.cpp378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters() argument
H A DMipsSEFrameLowering.cpp465 unsigned Reg1 = in emitPrologue() local
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
H A DMipsAsmPrinter.cpp874 EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2) EmitInstrRegReg() argument
894 EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg1, unsigned Reg2, unsigned Reg3) EmitInstrRegRegReg() argument
905 EmitMovFPIntPair(const MCSubtargetInfo &STI, unsigned MovOpc, unsigned Reg1, unsigned Reg2, unsigned FPReg1, unsigned FPReg2, bool LE) EmitMovFPIntPair() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp872 Register Reg1 = MI->getOperand(1).getReg(); in handleSpecialSwappables() local
H A DPPCRegisterInfo.cpp668 unsigned Reg1 = Reg; in lowerCRSpilling() local
713 unsigned Reg1 = Reg; in lowerCRRestore() local
817 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
H A DPPCInstrInfo.cpp396 Register Reg1 = MI.getOperand(1).getReg(); in commuteInstructionImpl() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp99 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch() local
H A DMipsTargetStreamer.cpp190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR() argument
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX() argument
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI() argument
242 emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0, int16_t Imm1, int16_t Imm2, SMLoc IDLoc, const MCSubtargetInfo *STI) emitRRIII() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
H A DMCRegisterInfo.h77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains() argument
740 uint16_t Reg1 = 0; member in llvm::MCRegUnitRootIterator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp783 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3, unsigned VM, bool Compr, unsigned Enabled, bool Done) buildEXP() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
H A DMCDwarf.cpp1335 unsigned Reg1 = Instr.getRegister(); in EmitCFIInstruction() local
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
519 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
557 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
568 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1867 invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, bool NeedsWinCFI) invalidateWindowsRegisterPairing() argument
1890 invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, bool UsesWinAAPCS, bool NeedsWinCFI, bool NeedsFrameRecord) invalidateRegisterPairing() argument
1906 unsigned Reg1 = AArch64::NoRegister; global() member
2131 unsigned Reg1 = RPI.Reg1; spillCalleeSavedRegisters() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp968 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) { in isRegIntersect() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp835 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, in parseAddress() argument
900 Register Reg1, Reg2; in parseAddress() local
1214 Register Reg1, Reg2; parseOperand() local
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