Searched defs:FCC0 (Results 1 - 4 of 4) sorted by relevance
| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | register-loong64.h | 132 enum CFRegister { FCC0, FCC1, FCC2, FCC3, FCC4, FCC5, FCC6, FCC7 }; enumerator
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| H A D | macro-assembler-loong64.h | 119 CompareF32(FPURegister cmp1, FPURegister cmp2, FPUCondition cc, CFRegister cd = FCC0) CompareF32() argument
124 CompareIsNanF32(FPURegister cmp1, FPURegister cmp2, CFRegister cd = FCC0) CompareIsNanF32() argument
129 CompareF64(FPURegister cmp1, FPURegister cmp2, FPUCondition cc, CFRegister cd = FCC0) CompareF64() argument
134 CompareIsNanF64(FPURegister cmp1, FPURegister cmp2, CFRegister cd = FCC0) CompareIsNanF64() argument
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 669 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in createCMovFP() local
2037 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); in lowerBRCOND() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 3940 Operand *FCC0 = OperandMIPS32FCC::create(getFunc(), OperandMIPS32FCC::FCC0); in lowerFcmp() local
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