Lines Matching defs:hw_cfg_cb
212 static bt_hw_cfg_cb_t hw_cfg_cb;
345 if (strstr(hw_cfg_cb.local_chip_name, p_entry->chipset_name) != NULL) {
487 hw_cfg_cb.state = HW_CFG_SET_BD_ADDR;
513 hw_cfg_cb.state = HW_CFG_READ_BD_ADDR;
634 switch (hw_cfg_cb.state) {
645 hw_cfg_cb.state = HW_CFG_READ_LOCAL_NAME;
659 strncpy(hw_cfg_cb.local_chip_name, p_name,
663 snprintf(hw_cfg_cb.local_chip_name,
665 strncpy(p_name, hw_cfg_cb.local_chip_name,
670 strncpy(hw_cfg_cb.local_chip_name, "UNKNOWN",
675 hw_cfg_cb.local_chip_name[LOCAL_NAME_BUFFER_LEN - 1] = 0;
677 BTHWDBG("Chipset %s", hw_cfg_cb.local_chip_name);
682 if ((hw_cfg_cb.fw_fd = open(p_name, O_RDONLY)) == -1) {
690 hw_cfg_cb.state = HW_CFG_DL_MINIDRIVER;
705 hw_cfg_cb.state = HW_CFG_DL_FW_PATCH;
709 p_buf->len = read(hw_cfg_cb.fw_fd, p, HCI_CMD_PREAMBLE_SIZE);
715 p_buf->len += read(hw_cfg_cb.fw_fd,
724 close(hw_cfg_cb.fw_fd);
725 hw_cfg_cb.fw_fd = -1;
737 hw_cfg_cb.f_set_baud_2 = TRUE;
749 hw_cfg_cb.state = HW_CFG_START;
761 hw_cfg_cb.state = HW_CFG_SET_UART_CLOCK;
777 hw_cfg_cb.state = (hw_cfg_cb.f_set_baud_2) ? HW_CFG_SET_UART_BAUD_2 : HW_CFG_SET_UART_BAUD_1;
802 hw_cfg_cb.state = 0;
804 if (hw_cfg_cb.fw_fd != -1) {
805 close(hw_cfg_cb.fw_fd);
806 hw_cfg_cb.fw_fd = -1;
834 hw_cfg_cb.state = 0;
836 if (hw_cfg_cb.fw_fd != -1) {
837 close(hw_cfg_cb.fw_fd);
838 hw_cfg_cb.fw_fd = -1;
844 } // switch(hw_cfg_cb.state)
859 if (hw_cfg_cb.fw_fd != -1) {
860 close(hw_cfg_cb.fw_fd);
861 hw_cfg_cb.fw_fd = -1;
864 hw_cfg_cb.state = 0;
1061 hw_cfg_cb.state = 0;
1062 hw_cfg_cb.fw_fd = -1;
1063 hw_cfg_cb.f_set_baud_2 = FALSE;
1083 hw_cfg_cb.state = HW_CFG_START;