Lines Matching defs:hw_cfg_cb
194 static bt_hw_cfg_cb_t hw_cfg_cb;
297 if (strstr(hw_cfg_cb.local_chip_name, p_entry->chipset_name) != NULL) {
439 hw_cfg_cb.state = HW_CFG_SET_BD_ADDR;
465 hw_cfg_cb.state = HW_CFG_READ_BD_ADDR;
584 switch (hw_cfg_cb.state) {
595 hw_cfg_cb.state = HW_CFG_READ_LOCAL_NAME;
609 strncpy(hw_cfg_cb.local_chip_name, p_name,
613 snprintf(hw_cfg_cb.local_chip_name,
615 strncpy(p_name, hw_cfg_cb.local_chip_name,
620 strncpy(hw_cfg_cb.local_chip_name, "UNKNOWN",
625 hw_cfg_cb.local_chip_name[LOCAL_NAME_BUFFER_LEN - 1] = 0;
627 BTHWDBG("Chipset %s", hw_cfg_cb.local_chip_name);
633 if ((hw_cfg_cb.fw_fd = open(p_name, O_RDONLY)) == -1) {
641 hw_cfg_cb.state = HW_CFG_DL_MINIDRIVER;
656 hw_cfg_cb.state = HW_CFG_DL_FW_PATCH;
660 p_buf->len = read(hw_cfg_cb.fw_fd, p, HCI_CMD_PREAMBLE_SIZE);
666 p_buf->len += read(hw_cfg_cb.fw_fd,
675 close(hw_cfg_cb.fw_fd);
676 hw_cfg_cb.fw_fd = -1;
688 hw_cfg_cb.f_set_baud_2 = TRUE;
701 hw_cfg_cb.state = HW_CFG_START;
713 hw_cfg_cb.state = HW_CFG_SET_UART_CLOCK;
729 hw_cfg_cb.state = (hw_cfg_cb.f_set_baud_2) ? HW_CFG_SET_UART_BAUD_2 : HW_CFG_SET_UART_BAUD_1;
755 hw_cfg_cb.state = 0;
757 if (hw_cfg_cb.fw_fd != -1) {
758 close(hw_cfg_cb.fw_fd);
759 hw_cfg_cb.fw_fd = -1;
791 hw_cfg_cb.state = 0;
793 if (hw_cfg_cb.fw_fd != -1) {
794 close(hw_cfg_cb.fw_fd);
795 hw_cfg_cb.fw_fd = -1;
801 } // switch(hw_cfg_cb.state)
817 if (hw_cfg_cb.fw_fd != -1) {
818 close(hw_cfg_cb.fw_fd);
819 hw_cfg_cb.fw_fd = -1;
822 hw_cfg_cb.state = 0;
1015 hw_cfg_cb.state = 0;
1016 hw_cfg_cb.fw_fd = -1;
1017 hw_cfg_cb.f_set_baud_2 = FALSE;
1037 hw_cfg_cb.state = HW_CFG_START;