Lines Matching refs:result
102 bitset128 result(mask);
105 result = (result << subgroupSize) | bitset128(mask);
107 return result;
1147 // the max number of outputs written. If it's false, store out the result
1876 // Simulate execution on the CPU, and compare against the GPU result
1890 const deUint64 *result = (const deUint64 *)ptrs[1];
1898 if (result[i] != ref[i])
1912 log << tcu::TestLog::Message << "result " << i << "(" << (i/invocationStride) << ", " << (i%invocationStride) << "): " << tcu::toHex(result[i]) << " ref " << tcu::toHex(ref[i]) << (result[i] != ref[i] ? " different" : "") << tcu::TestLog::EndMessage;
1921 // to have a corresponding fully converged output in the result. So walk through each lane's
1922 // results, and for each reference value of fullMask, find a corresponding result value of
1936 // For TT_SUCF_ELECT, when the reference result has a full mask, we expect lane 0 to be elected
1938 // expect a full mask. Search until we find the expected result with a matching store value in
1939 // the previous result.
1943 while (resLoc < maxLoc && !(result[resLoc] == expectedResult && result[resLoc-invocationStride] == ref[refLoc-invocationStride]))
1946 // If we didn't find this output in the result, flag it as an error.
1965 log << tcu::TestLog::Message << "result " << i << "(" << (i/invocationStride) << ", " << (i%invocationStride) << "): " << tcu::toHex(result[i]) << " ref " << tcu::toHex(ref[i]) << (i == firstFail[i%invocationStride] ? " first fail" : "") << tcu::TestLog::EndMessage;