Lines Matching refs:UVec3
232 const tcu::UVec3& numWorkGroups)
237 tcu::UVec3 m_numWorkGroups;
246 const tcu::UVec3 workGroupSize,
257 const tcu::UVec3 m_workGroupSize;
268 const tcu::UVec3& workGroupSize,
304 const tcu::UVec3 m_workGroupSize;
319 const tcu::UVec3& workGroupSize,
572 const tcu::UVec3 m_workGroupSize;
664 const tcu::UVec3& workGroupSize,
856 DispatchCaseDesc("single_invocation", INDIRECT_COMMAND_OFFSET, tcu::UVec3(1, 1, 1),
857 commandsVec(DispatchCommand(0, tcu::UVec3(1, 1, 1))), false
860 DispatchCaseDesc("multiple_groups", INDIRECT_COMMAND_OFFSET, tcu::UVec3(1, 1, 1),
861 commandsVec(DispatchCommand(0, tcu::UVec3(2, 3, 5))), false
864 DispatchCaseDesc("multiple_groups_multiple_invocations", INDIRECT_COMMAND_OFFSET, tcu::UVec3(2, 3, 1),
865 commandsVec(DispatchCommand(0, tcu::UVec3(1, 2, 3))), false
867 DispatchCaseDesc("small_offset", 16 + INDIRECT_COMMAND_OFFSET, tcu::UVec3(1, 1, 1),
868 commandsVec(DispatchCommand(16, tcu::UVec3(1, 1, 1))), false
870 DispatchCaseDesc("large_offset", (2 << 20), tcu::UVec3(1, 1, 1),
871 commandsVec(DispatchCommand((1 << 20) + 12, tcu::UVec3(1, 1, 1))), false
873 DispatchCaseDesc("large_offset_multiple_invocations", (2 << 20), tcu::UVec3(2, 3, 1),
874 commandsVec(DispatchCommand((1 << 20) + 12, tcu::UVec3(1, 2, 3))), false
876 DispatchCaseDesc("empty_command", INDIRECT_COMMAND_OFFSET, tcu::UVec3(1, 1, 1),
877 commandsVec(DispatchCommand(0, tcu::UVec3(0, 0, 0))), false
880 DispatchCaseDesc("multi_dispatch", 1 << 10, tcu::UVec3(3, 1, 2),
881 commandsVec(DispatchCommand(0, tcu::UVec3(1, 1, 1)),
882 DispatchCommand(INDIRECT_COMMAND_OFFSET, tcu::UVec3(2, 1, 1)),
883 DispatchCommand(104, tcu::UVec3(1, 3, 1)),
884 DispatchCommand(40, tcu::UVec3(1, 1, 7)),
885 DispatchCommand(52, tcu::UVec3(1, 1, 4))), false
888 DispatchCaseDesc("multi_dispatch_reuse_command", 1 << 10, tcu::UVec3(3, 1, 2),
889 commandsVec(DispatchCommand(0, tcu::UVec3(1, 1, 1)),
890 DispatchCommand(0, tcu::UVec3(1, 1, 1)),
891 DispatchCommand(0, tcu::UVec3(1, 1, 1)),
892 DispatchCommand(104, tcu::UVec3(1, 3, 1)),
893 DispatchCommand(104, tcu::UVec3(1, 3, 1)),
894 DispatchCommand(52, tcu::UVec3(1, 1, 4)),
895 DispatchCommand(52, tcu::UVec3(1, 1, 4))), false