Lines Matching refs:VIXL_ASSERT
97 VIXL_ASSERT(sizeof(dump_.d_[0]) == kDRegSizeInBytes);
98 VIXL_ASSERT(sizeof(dump_.s_[0]) == kSRegSizeInBytes);
99 VIXL_ASSERT(sizeof(dump_.h_[0]) == kHRegSizeInBytes);
100 VIXL_ASSERT(sizeof(dump_.d_[0]) == kXRegSizeInBytes);
101 VIXL_ASSERT(sizeof(dump_.s_[0]) == kWRegSizeInBytes);
102 VIXL_ASSERT(sizeof(dump_.x_[0]) == kXRegSizeInBytes);
103 VIXL_ASSERT(sizeof(dump_.w_[0]) == kWRegSizeInBytes);
104 VIXL_ASSERT(sizeof(dump_.q_[0]) == kQRegSizeInBytes);
121 VIXL_ASSERT(RegAliasesMatch(code));
129 VIXL_ASSERT(RegAliasesMatch(code));
135 VIXL_ASSERT(VRegAliasesMatch(code));
140 VIXL_ASSERT(VRegAliasesMatch(code));
153 VIXL_ASSERT(VRegAliasesMatch(code));
165 VIXL_ASSERT(VRegAliasesMatch(code));
166 VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
167 VIXL_ASSERT(lane < GetSVELaneCount(sizeof(T) * kBitsPerByte));
191 VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
192 VIXL_ASSERT(lane < GetSVELaneCount(p_bits_per_lane * kZRegBitsPerPRegBit));
196 VIXL_ASSERT(IsPowerOf2(p_bits_per_lane));
197 VIXL_ASSERT(p_bits_per_lane <= kChunkSizeInBits);
206 VIXL_ASSERT(lane_size_in_bits > 0);
207 VIXL_ASSERT((dump_.vl_ % lane_size_in_bits) == 0);
209 VIXL_ASSERT(count <= INT_MAX);
215 VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
221 VIXL_ASSERT(HasSVELane(reg, lane));
225 VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0);
236 VIXL_ASSERT(SPRegAliasesMatch());
241 VIXL_ASSERT(SPRegAliasesMatch());
247 VIXL_ASSERT(IsComplete());
248 VIXL_ASSERT((dump_.flags_ & ~Flags_mask) == 0);
262 VIXL_ASSERT(IsComplete());
263 VIXL_ASSERT(code < kNumberOfRegisters);
269 VIXL_ASSERT(IsComplete());
275 VIXL_ASSERT(IsComplete());
276 VIXL_ASSERT(code < kNumberOfVRegisters);
410 VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
411 VIXL_ASSERT(reg.HasLaneSize());
437 VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
438 VIXL_ASSERT(reg.HasLaneSize());
455 VIXL_ASSERT(result.IsZRegister() || result.IsPRegister());
456 VIXL_ASSERT(AreSameFormat(expected, result));