Lines Matching defs:reg
214 inline bool HasSVELane(T reg, int lane) const {
215 VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
216 return lane < GetSVELaneCount(reg.GetLaneSizeInBits());
220 inline uint64_t GetSVELane(T reg, int lane) const {
221 VIXL_ASSERT(HasSVELane(reg, lane));
222 if (reg.IsZRegister()) {
223 return zreg_lane(reg.GetCode(), reg.GetLaneSizeInBits(), lane);
224 } else if (reg.IsPRegister()) {
225 VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0);
226 return preg_lane(reg.GetCode(),
227 reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit,
356 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg);
359 const Register& reg,
382 const VRegister& reg);
395 const ZRegister& reg,
400 const PRegister& reg,
408 const R& reg,
410 VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
411 VIXL_ASSERT(reg.HasLaneSize());
415 if (!core->HasSVELane(reg, lane)) {
426 equal = EqualSVELane(expected[N - lane - 1], core, reg, lane) && equal;
435 const R& reg,
437 VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
438 VIXL_ASSERT(reg.HasLaneSize());
442 for (int lane = 0; lane < core->GetSVELaneCount(reg.GetLaneSizeInBits());
444 equal = EqualSVELane(expected, core, reg, lane) && equal;