Lines Matching defs:const
44 extern const double kFP64SignallingNaN;
45 extern const double kFP64QuietNaN;
48 extern const float kFP32SignallingNaN;
49 extern const float kFP32QuietNaN;
52 extern const Float16 kFP16SignallingNaN;
53 extern const Float16 kFP16QuietNaN;
61 T GetLane(int lane) const {
77 bool Equals(const VectorValue<kSizeInBytes>& other) const {
117 inline int32_t wreg(unsigned code) const {
125 inline int64_t xreg(unsigned code) const {
134 inline uint16_t hreg_bits(unsigned code) const {
139 inline uint32_t sreg_bits(unsigned code) const {
144 inline Float16 hreg(unsigned code) const {
148 inline float sreg(unsigned code) const {
152 inline uint64_t dreg_bits(unsigned code) const {
157 inline double dreg(unsigned code) const {
161 inline QRegisterValue qreg(unsigned code) const { return dump_.q_[code]; }
164 inline T zreg_lane(unsigned code, int lane) const {
173 int lane) const {
190 int lane) const {
195 const size_t kChunkSizeInBits = sizeof(Chunk) * kBitsPerByte;
205 inline int GetSVELaneCount(int lane_size_in_bits) const {
214 inline bool HasSVELane(T reg, int lane) const {
220 inline uint64_t GetSVELane(T reg, int lane) const {
235 inline int64_t spreg() const {
240 inline int32_t wspreg() const {
246 inline uint32_t flags_nzcv() const {
252 inline bool IsComplete() const { return completed_; }
261 bool RegAliasesMatch(unsigned code) const {
268 bool SPRegAliasesMatch() const {
274 bool VRegAliasesMatch(unsigned code) const {
295 CPUFeatures::Feature feature3 = CPUFeatures::kNone) const {
343 bool Equal32(uint32_t expected, const RegisterDump*, uint32_t result);
345 const RegisterDump*,
349 const RegisterDump*,
352 bool EqualFP16(Float16 expected, const RegisterDump*, uint16_t result);
353 bool EqualFP32(float expected, const RegisterDump*, float result);
354 bool EqualFP64(double expected, const RegisterDump*, double result);
356 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg);
358 const RegisterDump* core,
359 const Register& reg,
362 const RegisterDump* core,
363 const VRegister& vreg);
366 const RegisterDump* core,
367 const VRegister& fpreg);
369 const RegisterDump* core,
370 const VRegister& fpreg);
372 const RegisterDump* core,
373 const VRegister& fpreg);
375 bool Equal64(const Register& reg0,
376 const RegisterDump* core,
377 const Register& reg1,
381 const RegisterDump* core,
382 const VRegister& reg);
386 bool EqualRegisters(const RegisterDump* a, const RegisterDump* b);
389 bool NotEqual64(T0 reference, const RegisterDump* core, T1 result) {
394 const RegisterDump* core,
395 const ZRegister& reg,
399 const RegisterDump* core,
400 const PRegister& reg,
406 bool EqualSVE(const T (&expected)[N],
407 const RegisterDump* core,
408 const R& reg,
434 const RegisterDump* core,
435 const R& reg,
451 bool EqualSVE(const R& expected,
452 const RegisterDump* core,
453 const R& result,
474 bool EqualMemory(const void* expected,
475 const void* result,
514 uint64_t const value = 0xfedcba9876543210);
519 double const value = kFP64SignallingNaN);
536 void CalculateSVEAddress(const Register& xd,
537 const SVEMemOperand& addr,
542 void CalculateSVEAddress(const Register& xd, const SVEMemOperand& addr) {
580 bool CanRun(const CPUFeatures& required, bool* queried_can_run = NULL);
584 static const CPUFeatures kInfrastructureCPUFeatures(CPUFeatures::kNEON);
603 // function receives a `const Test& config` argument, to allow it to query the
629 static const int kSVEVectorLengthInBits =
661 const ZRegister& zdn,
662 const T (&values)[N]) {