Lines Matching refs:zm
382 ZRegister zm = z3.WithLaneSize(lane_size_in_bits);
388 InsrHelper(&masm, zm, zm_inputs);
408 __ Mla(mla_da_result, p0.Merging(), mla_da_result, zn, zm);
411 __ Mla(mla_dn_result, p1.Merging(), za, mla_dn_result, zm);
413 __ Mov(mla_dm_result, zm);
417 __ Mla(mla_d_result, p3.Merging(), za, zn, zm);
427 __ Mls(mls_da_result, p0.Merging(), mls_da_result, zn, zm);
430 __ Mls(mls_dn_result, p1.Merging(), za, mls_dn_result, zm);
432 __ Mov(mls_dm_result, zm);
436 __ Mls(mls_d_result, p3.Merging(), za, zn, zm);
4472 const ZRegister& zm);
4500 // `instr` zd(dst), zm(src_a), zd(src_b)
4501 // Based on whether zd and zm registers are aliased, the macro of instructions
4507 // `instr` zd(dst), zm(src_a), zn(src_b)
5034 const ZRegister& zm);
5047 ZRegister zm = z27.WithLaneSize(lane_size_in_bits);
5049 InsrHelper(&masm, zm, zm_inputs);
5052 (masm.*macro)(zd, zn, zm);
11627 const ZRegister& zm,
11632 __ Sdot(zd, za, zn, zm);
11634 __ Sdot(zd, za, zn, zm, index_fn);
11638 __ Udot(zd, za, zn, zm);
11640 __ Udot(zd, za, zn, zm, index_fn);
11648 ZRegister zm = z3.WithLaneSize(lane_size_in_bits / 4);
11653 InsrHelper(&masm, zm, zm_inputs);
11663 // zda = zda + (zn . zm)
11664 dot_fn(da_result, da_result, zn, zm, is_signed, index);
11667 // zdn = za + (zdn . zm)
11668 dot_fn(dn_result, za, dn_result.WithSameLaneSizeAs(zn), zm, is_signed, index);
11670 __ Mov(dm_result, zm.WithSameLaneSizeAs(dm_result));
11672 dot_fn(dm_result, za, zn, dm_result.WithSameLaneSizeAs(zm), is_signed, index);
11675 // zd = za + (zn . zm)
11676 dot_fn(d_result, za, zn, zm, is_signed, index);
11683 dnm_result.WithSameLaneSizeAs(zm),
11790 int64_t zd_expected_s[][s] = {{0, 1, 2, 3}, // Generated from zm[0]
11824 int64_t zd_expected_d[][d] = {{-508, -507}, // Generated from zm[0]
12112 ZRegister zm = z31.WithLaneSize(lane_size_in_bits);
12121 InsrHelper(&masm, zm, zm_rawbits);
12123 (masm.*macro)(zd, zn, zm);
12270 const ZRegister& zm,
12277 const ZRegister& zm);
12298 ZRegister zm = z28.WithLaneSize(lane_size_in_bits);
12309 InsrHelper(&masm, zm, zm_inputs_rawbits);
12315 // `instr` zdn, pg, zdn, zm
12319 (masm.*macro)(dn_result, pg.Merging(), dn_result, zm, nan_option);
12321 (masm.*macro_nonan)(dn_result, pg.Merging(), dn_result, zm);
12324 // Based on whether zd and zm registers are aliased, the macro of instructions
12329 __ Mov(dm_result, zm);
12341 // `instr` zd, pg, zn, zm
12345 (masm.*macro)(d_result, pg.Merging(), zn, zm, nan_option);
12347 (masm.*macro_nonan)(d_result, pg.Merging(), zn, zm);
12809 ZRegister zm = z28.WithLaneSize(kDRegSize);
12812 InsrHelper(&masm, zm, zm_inputs);
12814 (masm.*macro)(zd, zn, zm);
16636 const ZRegister& zm,
16659 ZRegister zm = z3.WithLaneSize(lane_size_in_bits);
16671 InsrHelper(&masm, zm, zm_rawbits);
16691 (masm.*macro)(da_result, p0.Merging(), da_result, zn, zm, nan_option);
16694 (masm.*macro)(dn_result, p0.Merging(), za, dn_result, zm, nan_option);
16696 __ Mov(dm_result, zm);
16700 (masm.*macro)(d_result, p0.Merging(), za, zn, zm, nan_option);
16709 ASSERT_EQUAL_SVE(zm_rawbits, zm);
16730 // fmla : zd = za + zn * zm
16781 // fmls : zd = za - zn * zm
16832 // fnmla : zd = -za - zn * zm
16883 // fnmls : zd = -za + zn * zm
16936 const ZRegister& zm,
16962 (masm.*macro_idx)(z3.VnH(), z2.VnH(), z1.VnH(), z3.VnH(), 0); // zd == zm
16972 (masm.*macro_idx)(z7.VnS(), z2.VnS(), z1.VnS(), z7.VnS(), 0); // zd == zm
16982 (masm.*macro_idx)(z11.VnD(), z2.VnD(), z1.VnD(), z11.VnD(), 0); // zd == zm
16988 // zd == zn == zm
17688 const ZRegister& zm);
17698 const ZRegister& zm);
17871 double zm[] = {-0.0, inf_n, inf_n, -2.0, inf_n, nan, nan, inf_p};
17890 TestFpCompareHelper(config, lane_size, gt, zn, zm, pd_fcm_gt);
17891 TestFpCompareHelper(config, lane_size, lt, zn, zm, pd_fcm_lt);
17892 TestFpCompareHelper(config, lane_size, ge, zn, zm, pd_fcm_ge);
17893 TestFpCompareHelper(config, lane_size, le, zn, zm, pd_fcm_le);
17894 TestFpCompareHelper(config, lane_size, eq, zn, zm, pd_fcm_eq);
17895 TestFpCompareHelper(config, lane_size, ne, zn, zm, pd_fcm_ne);
17896 TestFpCompareHelper(config, lane_size, uo, zn, zm, pd_fcm_uo);
17899 TestFpCompareHelper(config, lane_size, gt, zn, zm, pd_fac_gt, true);
17900 TestFpCompareHelper(config, lane_size, lt, zn, zm, pd_fac_lt, true);
17901 TestFpCompareHelper(config, lane_size, ge, zn, zm, pd_fac_ge, true);
17902 TestFpCompareHelper(config, lane_size, le, zn, zm, pd_fac_le, true);
18801 {8, // 2 * zn[11] * zm[8] = 2 * 4 * 1
18802 24, // 2 * zn[9] * zm[8] = 2 * 4 * 3
18803 80, // 2 * zn[7] * zm[4] = 2 * 8 * 5
18804 112, // 2 * zn[5] * zm[4] = 2 * 8 * 7
18805 0x7fffffffffffffff, // 2 * zn[3] * zm[0]
18806 0x8000000100000000}; // 2 * zn[1] * zm[0]
18858 {-11, // za.d[5] + 2 * zn.s[10] * zm.s[8] = 5 + 2 * -2 * 4
18859 -28, // za.d[4] + 2 * zn.s[8] * zm.s[8] = 4 + 2 * -4 * 4
18860 -93, // za.d[3] + 2 * zn.s[6] * zm.s[4] = 3 + 2 * -6 * 8
18861 -126, // za.d[2] + 2 * zn.s[4] * zm.s[4] = 2 + 2 * -8 * 8
18866 {1, // za.d[5] + 2 * zn.s[11] * zm.s[9] = -5 + 2 * 1 * 3
18867 14, // za.d[4] + 2 * zn.s[9] * zm.s[9] = -4 + 2 * 3 * 3
18868 67, // za.d[3] + 2 * zn.s[7] * zm.s[5] = -3 + 2 * 5 * 7
18869 96, // za.d[2] + 2 * zn.s[5] * zm.s[5] = -2 + 2 * 7 * 7