Lines Matching refs:zd
379 ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
385 InsrHelper(&masm, zd, zd_inputs);
416 __ Mov(mla_d_result, zd);
435 __ Mov(mls_d_result, zd);
4469 typedef void (MacroAssembler::*ArithPredicatedFn)(const ZRegister& zd,
4496 // `instr` zd(dst), zd(src_a), zn(src_b)
4500 // `instr` zd(dst), zm(src_a), zd(src_b)
4501 // Based on whether zd and zm registers are aliased, the macro of instructions
4507 // `instr` zd(dst), zm(src_a), zn(src_b)
4509 // and movprfx + `instr` based on whether zd and zn registers are aliased.
5032 typedef void (MacroAssembler::*ArithFn)(const ZRegister& zd,
5051 ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
5052 (masm.*macro)(zd, zn, zm);
5058 ASSERT_EQUAL_SVE(zd_expected, zd);
10776 typedef void (MacroAssembler::*IntWideImmFn)(const ZRegister& zd,
11624 auto dot_fn = [&](const ZRegister& zd,
11632 __ Sdot(zd, za, zn, zm);
11634 __ Sdot(zd, za, zn, zm, index_fn);
11638 __ Udot(zd, za, zn, zm);
11640 __ Udot(zd, za, zn, zm, index_fn);
11645 ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
11650 InsrHelper(&masm, zd, zd_inputs);
11674 __ Mov(d_result, zd);
11675 // zd = za + (zn . zm)
12110 ZRegister zd = z29.WithLaneSize(lane_size_in_bits);
12123 (masm.*macro)(zd, zn, zm);
12130 ASSERT_EQUAL_SVE(zd_expected, zd);
12267 const ZRegister& zd,
12274 const ZRegister& zd,
12296 ZRegister zd = z26.WithLaneSize(lane_size_in_bits);
12310 InsrHelper(&masm, zd, zd_inputs_rawbits);
12324 // Based on whether zd and zm registers are aliased, the macro of instructions
12337 // and movprfx + `instr` based on whether zd and zn registers are aliased.
12341 // `instr` zd, pg, zn, zm
12343 __ Mov(d_result, zd);
12807 ZRegister zd = z26.WithLaneSize(lane_size_in_bits);
12814 (masm.*macro)(zd, zn, zm);
12833 ASSERT_EQUAL_SVE(zd_expected, zd);
15346 typedef void (MacroAssembler::*FcvtFrintMFn)(const ZRegister& zd,
15350 typedef void (MacroAssembler::*FcvtFrintZFn)(const ZRegister& zd,
16632 const ZRegister& zd,
16656 ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
16673 // Initialize `zd` with a signalling NaN.
16676 __ Dup(zd, x29);
16699 __ Mov(d_result, zd);
16730 // fmla : zd = za + zn * zm
16781 // fmls : zd = za - zn * zm
16832 // fnmla : zd = -za - zn * zm
16883 // fnmls : zd = -za + zn * zm
16933 typedef void (MacroAssembler::*FPMulAccIdxFn)(const ZRegister& zd,
16962 (masm.*macro_idx)(z3.VnH(), z2.VnH(), z1.VnH(), z3.VnH(), 0); // zd == zm
16964 (masm.*macro_idx)(z4.VnH(), z2.VnH(), z4.VnH(), z0.VnH(), 1); // zd == zn
16966 (masm.*macro_idx)(z5.VnH(), z5.VnH(), z1.VnH(), z0.VnH(), 4); // zd == za
16972 (masm.*macro_idx)(z7.VnS(), z2.VnS(), z1.VnS(), z7.VnS(), 0); // zd == zm
16974 (masm.*macro_idx)(z8.VnS(), z2.VnS(), z8.VnS(), z0.VnS(), 1); // zd == zn
16976 (masm.*macro_idx)(z9.VnS(), z9.VnS(), z1.VnS(), z0.VnS(), 2); // zd == za
16982 (masm.*macro_idx)(z11.VnD(), z2.VnD(), z1.VnD(), z11.VnD(), 0); // zd == zm
16984 (masm.*macro_idx)(z12.VnD(), z2.VnD(), z12.VnD(), z0.VnD(), 1); // zd == zn
16986 (masm.*macro_idx)(z13.VnD(), z13.VnD(), z1.VnD(), z0.VnD(), 0); // zd == za
16988 // zd == zn == zm
17133 // With an all-true predicate, the value in zd is
17146 // With an all-true predicate, the value in zd is
17995 typedef void (MacroAssembler::*FPUnaryMFn)(const ZRegister& zd,
17999 typedef void (MacroAssembler::*FPUnaryZFn)(const ZRegister& zd,
18095 // Check in-place operation where zd == zn.