Lines Matching refs:Lsl
10709 __ Lsl(zn_s, zn_s, kSRegSize);
12700 __ Lsl(zd_lsl, zn, shift - 1); // Lsl supports 0 - lane_size-1.
12799 macro = &MacroAssembler::Lsl;
12994 __ Lsl(z3.VnB(), p0.Merging(), z0.VnB(), z1.VnB());
13000 __ Lsl(z6.VnH(), p3.Merging(), z0.VnH(), z1.VnH());
13006 __ Lsl(z9.VnS(), p0.Merging(), z0.VnS(), z1.VnS());
13011 __ Lsl(z12.VnD(), p0.Merging(), z0.VnD(), z1.VnD());
13015 __ Lsl(z14.VnD(), p0.Merging(), z1.VnD(), z11.VnD());
13069 __ Lsl(z3.VnB(), p0.Merging(), z0.VnB(), z1.VnD());
13074 __ Lsl(z6.VnH(), p3.Merging(), z6.VnH(), z1.VnD());
13079 __ Lsl(z9.VnS(), p0.Merging(), z0.VnS(), z1.VnD());
13121 __ Lsl(z1.VnB(), p2.Merging(), z1.VnB(), 1);
13126 __ Lsl(z4.VnH(), p3.Merging(), z4.VnH(), 2);
13131 __ Lsl(z7.VnS(), p4.Merging(), z7.VnS(), 3);
13136 __ Lsl(z10.VnD(), p5.Merging(), z10.VnD(), 4);
19211 __ Lsl(z0.VnS(), z0.VnS(), shift);
19212 __ Lsl(z1.VnS(), z1.VnS(), shift);