Lines Matching defs:all
354 // Check that the upper lanes are all clear.
1535 // With an all-true predicate, these instructions increment or decrement by
1625 // With an all-true predicate, these instructions increment or decrement by
1666 // Check all-true predicates.
1735 // With an all-true predicate, these instructions increment or decrement by
1775 // Check all-true predicates.
1884 // With an all-true predicate, these instructions increment or decrement by
2032 // With an all-true predicate, these instructions increment or decrement by
2188 // With an all-true predicate, these instructions increment or decrement by
2701 // As above, but with all flags initially set.
2919 // If pg is all inactive, the input is passed through unchanged.
2936 // Check that the Simulator behaves correctly when all arguments are aliased.
2997 // element in pn. If all pn elements are false (as in in0), it starts looking
3083 // element in pn. If all pn elements are false (as in in0), it starts looking
3171 // element in pn. If all pn elements are false (as in in0), it starts looking
3236 // element in pn. If all pn elements are false (as in in0), it starts looking
3277 // Check that the Simulator behaves correctly when all arguments are aliased.
3425 int all = core.GetSVELaneCount(lane_size_in_bits);
3426 int pow2 = 1 << HighestSetBitPosition(all);
3427 int mul4 = all - (all % 4);
3428 int mul3 = all - (all % 3);
3431 for (int i = 0; i < all; i++) {
3433 ASSERT_EQUAL_SVE_LANE((all >= 1) && (i < 1), p[1], i);
3434 ASSERT_EQUAL_SVE_LANE((all >= 2) && (i < 2), p[2], i);
3435 ASSERT_EQUAL_SVE_LANE((all >= 5) && (i < 5), p[3], i);
3436 ASSERT_EQUAL_SVE_LANE((all >= 6) && (i < 6), p[4], i);
3437 ASSERT_EQUAL_SVE_LANE((all >= 8) && (i < 8), p[5], i);
3438 ASSERT_EQUAL_SVE_LANE((all >= 16) && (i < 16), p[6], i);
3439 ASSERT_EQUAL_SVE_LANE((all >= 64) && (i < 64), p[7], i);
3440 ASSERT_EQUAL_SVE_LANE((all >= 256) && (i < 256), p[8], i);
3463 ASSERT_EQUAL_64((all >= 1) ? nonzero : zero, x1);
3464 ASSERT_EQUAL_64((all >= 2) ? nonzero : zero, x2);
3465 ASSERT_EQUAL_64((all >= 5) ? nonzero : zero, x3);
3466 ASSERT_EQUAL_64((all >= 6) ? nonzero : zero, x4);
3467 ASSERT_EQUAL_64((all >= 8) ? nonzero : zero, x5);
3468 ASSERT_EQUAL_64((all >= 16) ? nonzero : zero, x6);
3469 ASSERT_EQUAL_64((all >= 64) ? nonzero : zero, x7);
3470 ASSERT_EQUAL_64((all >= 256) ? nonzero : zero, x8);
3477 ASSERT_EQUAL_64((all >= 4) ? nonzero : zero, x13);
3478 ASSERT_EQUAL_64((all >= 3) ? nonzero : zero, x14);
3594 // If pg is all inactive, the value of pn is irrelevant.
3631 // With an all-true predicate, these instructions measure the vector length.
3637 // `ptrue p10.b` provides an all-active pg.
3669 // Check all-active predicates in various combinations.
3767 int all = core.GetSVELaneCount(lane_size_in_bits);
3768 int pow2 = 1 << HighestSetBitPosition(all);
3769 int mul4 = all - (all % 4);
3770 int mul3 = all - (all % 3);
3775 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(1, all)), x1);
3776 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(2, all)), x2);
3777 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(3, all)), x3);
3778 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(4, all)), x4);
3779 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(5, all)), x5);
3780 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(6, all)), x6);
3781 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(7, all)), x7);
3782 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(8, all)), x8);
3783 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(16, all)), x9);
3784 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(32, all)), x10);
3785 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(64, all)), x11);
3786 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(128, all)), x12);
3787 ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(256, all)), x13);
3793 ASSERT_EQUAL_64(acc_value + (multiplier * all), x21);
3930 int all = core.GetSVELaneCount(lane_size_in_bits);
3931 int pow2 = 1 << HighestSetBitPosition(all);
3932 int mul4 = all - (all % 4);
3933 int mul3 = all - (all % 3);
3938 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(1, all)), x1);
3939 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(2, all)), x2);
3940 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(3, all)), x3);
3941 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(4, all)), x4);
3942 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(5, all)), x5);
3943 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(6, all)), x6);
3944 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(7, all)), x7);
3945 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(8, all)), x8);
3946 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(16, all)), x9);
3947 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(32, all)), x10);
3948 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(64, all)), x11);
3949 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(128, all)), x12);
3950 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(256, all)), x13);
3956 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * all), x21);
4221 int all = core.GetSVELaneCount(lane_size_in_bits);
4222 int pow2 = 1 << HighestSetBitPosition(all);
4223 int mul4 = all - (all % 4);
4224 int mul3 = all - (all % 3);
4229 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(1, all)), x1);
4230 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(2, all)), x2);
4231 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(3, all)), x3);
4232 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(4, all)), x4);
4233 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(5, all)), x5);
4234 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(6, all)), x6);
4235 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(7, all)), x7);
4236 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(8, all)), x8);
4237 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(16, all)), x9);
4238 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(32, all)), x10);
4239 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(64, all)), x11);
4240 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(128, all)), x12);
4241 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(256, all)), x13);
4247 ASSERT_EQUAL_64(QAdd(acc_value, multiplier * all), x21);
8825 PRegister all = p7;
8826 __ Ptrue(all.VnB());
8867 all.Zeroing(),
8933 all.Zeroing(),
8937 __ Rdffrs(p0.VnB(), all.Zeroing());
8943 ldff1)(z16.WithLaneSize(esize_in_bits), all.Zeroing(), SVEMemOperand(x20));
8944 __ Rdffrs(p1.VnB(), all.Zeroing());
8945 __ Cntp(x0, all, p1.VnB());
8962 __ Not(p0.VnB(), all.Zeroing(), p0.VnB());
9468 PRegister all = p6;
9469 __ Ptrue(all.VnB());
9478 __ Ldff1b(z1.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
9479 __ Ldff1h(z2.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
9480 __ Ldff1w(z3.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
9481 __ Ldff1sb(z4.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
9482 __ Ldff1sh(z5.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
9485 __ Ldff1h(z6.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 1));
9486 __ Ldff1w(z7.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 2));
9487 __ Ldff1sh(z8.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW, 1));
9500 __ Ldff1b(z9.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9501 __ Ldff1h(z10.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
9502 __ Ldff1w(z11.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9503 __ Ldff1sb(z12.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9504 __ Ldff1sh(z13.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
9505 __ Ldff1sw(z14.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9508 __ Ldff1h(z15.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
9509 __ Ldff1w(z16.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
9510 __ Ldff1d(z17.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 3));
9511 __ Ldff1sh(z18.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
9512 __ Ldff1sw(z19.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
9519 __ Ldff1b(z20.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9520 __ Ldff1h(z21.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9521 __ Ldff1w(z22.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9522 __ Ldff1sh(z23.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9523 __ Ldff1sw(z24.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9528 __ Ldff1h(z25.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
9529 __ Ldff1sh(z26.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
9533 __ Ldff1w(z27.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
9534 __ Ldff1sw(z28.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
9538 __ Ldff1d(z29.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 3));
9541 __ Cntp(x10, all, p1.VnB());
9551 // Report a warning when we hit fault-tolerant loads before all expected
9664 PRegister all = p6;
9665 __ Ptrue(all.VnB());
9672 __ Ld1b(z1.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
9673 __ Ld1h(z2.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
9674 __ Ld1w(z3.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
9675 __ Ld1sb(z4.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
9676 __ Ld1sh(z5.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
9679 __ Ld1h(z6.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 1));
9680 __ Ld1w(z7.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 2));
9681 __ Ld1sh(z8.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW, 1));
9694 __ Ld1b(z9.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9695 __ Ld1h(z10.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
9696 __ Ld1w(z11.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9697 __ Ld1sb(z12.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9698 __ Ld1sh(z13.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
9699 __ Ld1sw(z14.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
9702 __ Ld1h(z15.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
9703 __ Ld1w(z16.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
9704 __ Ld1d(z17.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 3));
9705 __ Ld1sh(z18.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
9706 __ Ld1sw(z19.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
9713 __ Ld1b(z20.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9714 __ Ld1h(z21.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9715 __ Ld1w(z22.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9716 __ Ld1sh(z23.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9717 __ Ld1sw(z24.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
9722 __ Ld1h(z25.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
9723 __ Ld1sh(z26.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
9727 __ Ld1w(z27.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
9728 __ Ld1sw(z28.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
9732 __ Ld1d(z29.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 3));
9871 PRegister all = p6;
9872 __ Ptrue(all.WithLaneSize(esize_in_bits));
9912 __ Rdffrs(pg_ff.VnB(), all.Zeroing());
9913 __ Cmpeq(pg_diff, all.Zeroing(), zt_ref, zt_ff);
9914 __ Eor(pg_diff.VnB(), all.Zeroing(), pg_diff.VnB(), pg_ff.VnB());
10412 // Store with all-true and patterned predication, load back, and create a
10490 // Check that all segments match by rotating the vector by one segment,
11377 // Check the upper lanes above the top of the V register are all clear.
11451 // Check the upper lanes above the top of the V register are all clear.
11523 // Check the upper lanes above the top of the V register are all clear.
11595 // Check the upper lanes above the top of the V register are all clear.
11991 // Negate the all positive vector for testing signed dot.
13444 // The last active element of `pn` are `true` in all vector length configurations.
13501 // The last active element of `pn` are `false` in all vector length configurations.
13516 // The last active element of `pn` are `true` in all vector length configurations.
13573 // The last active element of `pn` are `false` in all vector length configurations.
14225 // The all-inactive zeroing predicate sets destination predicate all-false.
14291 // The all-inactive zeroing predicate sets destination predicate all-false.
15384 // Test floating-point conversions with all lanes activated.
15938 // Test integer conversions with all lanes activated.
16270 // Note that IEEE 754 double-precision format has 52-bits fraction, so all
16641 // expected result on all-true predication.
17096 // Execute a number of instructions which all use ProcessNaNs, and check that
17097 // they all propagate NaNs correctly.
17121 // With an all-true predicate, this helper aims to compare with special
17133 // With an all-true predicate, the value in zd is
17146 // With an all-true predicate, the value in zd is
17169 // With an all-true predicate, this helper aims to compare with special
18038 // Run the operation on all lanes.
18083 // Check all lanes.
20116 // Check that all 256-bit segments match by rotating the vector by one