Lines Matching refs:Is
193 VIXL_CHECK(NoReg.Is(NoVReg));
194 VIXL_CHECK(NoVReg.Is(NoReg));
196 VIXL_CHECK(NoVReg.Is(NoReg));
197 VIXL_CHECK(NoReg.Is(NoVReg));
199 VIXL_CHECK(NoReg.Is(NoCPUReg));
200 VIXL_CHECK(NoCPUReg.Is(NoReg));
202 VIXL_CHECK(NoVReg.Is(NoCPUReg));
203 VIXL_CHECK(NoCPUReg.Is(NoVReg));
205 VIXL_CHECK(NoVReg.Is(NoCPUReg));
206 VIXL_CHECK(NoCPUReg.Is(NoVReg));
216 VIXL_CHECK(WRegister(0).Is(w0));
217 VIXL_CHECK(XRegister(1).Is(x1));
219 VIXL_CHECK(BRegister(2).Is(b2));
220 VIXL_CHECK(HRegister(3).Is(h3));
221 VIXL_CHECK(SRegister(4).Is(s4));
222 VIXL_CHECK(DRegister(5).Is(d5));
223 VIXL_CHECK(QRegister(6).Is(q6));
225 VIXL_CHECK(ZRegister(7).Is(z7));
226 VIXL_CHECK(PRegister(8).Is(p8));
232 VIXL_CHECK(Register(0, kWRegSize).Is(w0));
233 VIXL_CHECK(Register(1, kXRegSize).Is(x1));
239 VIXL_CHECK(VRegister(0).Is(v0));
240 VIXL_CHECK(VRegister(1).Is(v1));
241 VIXL_CHECK(VRegister(2).Is(v2));
242 VIXL_CHECK(VRegister(3).Is(v3));
243 VIXL_CHECK(VRegister(4).Is(v4));
246 VIXL_CHECK(VRegister(0, kBRegSize).Is(b0));
247 VIXL_CHECK(VRegister(1, kHRegSize).Is(h1));
248 VIXL_CHECK(VRegister(2, kSRegSize).Is(s2));
249 VIXL_CHECK(VRegister(3, kDRegSize).Is(d3));
250 VIXL_CHECK(VRegister(4, kQRegSize).Is(q4));
253 VIXL_CHECK(VRegister(0, kBRegSize, 1).Is(b0));
254 VIXL_CHECK(VRegister(1, kHRegSize, 1).Is(h1));
255 VIXL_CHECK(VRegister(2, kSRegSize, 1).Is(s2));
256 VIXL_CHECK(VRegister(3, kDRegSize, 1).Is(d3));
257 VIXL_CHECK(VRegister(4, kQRegSize, 1).Is(q4));
259 VIXL_CHECK(VRegister(0, kSRegSize, 2).Is(v0.V2H()));
261 VIXL_CHECK(VRegister(1, kDRegSize, 1).Is(v1.V1D()));
262 VIXL_CHECK(VRegister(2, kDRegSize, 2).Is(v2.V2S()));
263 VIXL_CHECK(VRegister(3, kDRegSize, 4).Is(v3.V4H()));
264 VIXL_CHECK(VRegister(4, kDRegSize, 8).Is(v4.V8B()));
266 VIXL_CHECK(VRegister(5, kQRegSize, 2).Is(v5.V2D()));
267 VIXL_CHECK(VRegister(6, kQRegSize, 4).Is(v6.V4S()));
268 VIXL_CHECK(VRegister(7, kQRegSize, 8).Is(v7.V8H()));
269 VIXL_CHECK(VRegister(8, kQRegSize, 16).Is(v8.V16B()));
272 VIXL_CHECK(VRegister(0, kFormatB).Is(b0));
273 VIXL_CHECK(VRegister(1, kFormatH).Is(h1));
274 VIXL_CHECK(VRegister(2, kFormatS).Is(s2));
275 VIXL_CHECK(VRegister(3, kFormatD).Is(d3));
276 VIXL_CHECK(VRegister(4, kFormat8B).Is(v4.V8B()));
277 VIXL_CHECK(VRegister(5, kFormat16B).Is(v5.V16B()));
278 VIXL_CHECK(VRegister(6, kFormat2H).Is(v6.V2H()));
279 VIXL_CHECK(VRegister(7, kFormat4H).Is(v7.V4H()));
280 VIXL_CHECK(VRegister(8, kFormat8H).Is(v8.V8H()));
281 VIXL_CHECK(VRegister(9, kFormat2S).Is(v9.V2S()));
282 VIXL_CHECK(VRegister(10, kFormat4S).Is(v10.V4S()));
283 VIXL_CHECK(VRegister(11, kFormat1D).Is(v11.V1D()));
284 VIXL_CHECK(VRegister(12, kFormat2D).Is(v12.V2D()));
290 VIXL_CHECK(ZRegister(0, kBRegSize).Is(z0.VnB()));
291 VIXL_CHECK(ZRegister(1, kHRegSize).Is(z1.VnH()));
292 VIXL_CHECK(ZRegister(2, kSRegSize).Is(z2.VnS()));
293 VIXL_CHECK(ZRegister(3, kDRegSize).Is(z3.VnD()));
296 VIXL_CHECK(ZRegister(0, kFormatVnB).Is(z0.VnB()));
297 VIXL_CHECK(ZRegister(1, kFormatVnH).Is(z1.VnH()));
298 VIXL_CHECK(ZRegister(2, kFormatVnS).Is(z2.VnS()));
299 VIXL_CHECK(ZRegister(3, kFormatVnD).Is(z3.VnD()));
305 VIXL_CHECK(PRegisterWithLaneSize(0, kBRegSize).Is(p0.VnB()));
306 VIXL_CHECK(PRegisterWithLaneSize(1, kHRegSize).Is(p1.VnH()));
307 VIXL_CHECK(PRegisterWithLaneSize(2, kSRegSize).Is(p2.VnS()));
308 VIXL_CHECK(PRegisterWithLaneSize(3, kDRegSize).Is(p3.VnD()));
311 VIXL_CHECK(PRegisterWithLaneSize(0, kFormatVnB).Is(p0.VnB()));
312 VIXL_CHECK(PRegisterWithLaneSize(1, kFormatVnH).Is(p1.VnH()));
313 VIXL_CHECK(PRegisterWithLaneSize(2, kFormatVnS).Is(p2.VnS()));
314 VIXL_CHECK(PRegisterWithLaneSize(3, kFormatVnD).Is(p3.VnD()));
316 VIXL_CHECK(PRegisterZ(0).Is(p0.Zeroing()));
317 VIXL_CHECK(PRegisterM(1).Is(p1.Merging()));
323 VIXL_CHECK(CPURegister(0, kWRegSize, CPURegister::kRegister).Is(w0));
324 VIXL_CHECK(CPURegister(1, kXRegSize, CPURegister::kRegister).Is(x1));
326 VIXL_CHECK(CPURegister(2, kBRegSize, CPURegister::kVRegister).Is(b2));
327 VIXL_CHECK(CPURegister(3, kHRegSize, CPURegister::kVRegister).Is(h3));
328 VIXL_CHECK(CPURegister(4, kSRegSize, CPURegister::kVRegister).Is(s4));
329 VIXL_CHECK(CPURegister(5, kDRegSize, CPURegister::kVRegister).Is(d5));
330 VIXL_CHECK(CPURegister(6, kQRegSize, CPURegister::kVRegister).Is(q6));
331 VIXL_CHECK(CPURegister(7, kQRegSize, CPURegister::kVRegister).Is(v7));
334 .Is(z0));
336 .Is(p1));
366 VIXL_CHECK(out.Is(reg));
601 VIXL_CHECK(z0.Is(z0));
602 VIXL_CHECK(!z0.Is(z1));
603 VIXL_CHECK(!z0.Is(v0));
604 VIXL_CHECK(!z0.Is(b0));
605 VIXL_CHECK(!z0.Is(q0));
631 VIXL_ASSERT(v6.B().Is(b6));
632 VIXL_ASSERT(v7.H().Is(h7));
633 VIXL_ASSERT(v8.S().Is(s8));
634 VIXL_ASSERT(v9.D().Is(d9));
636 VIXL_ASSERT(z6.B().Is(b6));
637 VIXL_ASSERT(z7.H().Is(h7));
638 VIXL_ASSERT(z8.S().Is(s8));
639 VIXL_ASSERT(z9.D().Is(d9));
645 // Test that the variants can be distinguished with `Is`.
646 VIXL_CHECK(!z6.VnB().Is(b6));
647 VIXL_CHECK(!z7.VnH().Is(h7));
648 VIXL_CHECK(!z8.VnS().Is(s8));
649 VIXL_CHECK(!z9.VnD().Is(d9));
651 VIXL_CHECK(!z6.VnB().Is(v6.B()));
652 VIXL_CHECK(!z7.VnH().Is(v7.H()));
653 VIXL_CHECK(!z8.VnS().Is(v8.S()));
654 VIXL_CHECK(!z9.VnD().Is(v9.D()));
656 VIXL_CHECK(!z6.VnB().Is(z6.B()));
657 VIXL_CHECK(!z7.VnH().Is(z7.H()));
658 VIXL_CHECK(!z8.VnS().Is(z8.S()));
659 VIXL_CHECK(!z9.VnD().Is(z9.D()));
955 VIXL_CHECK(r_x0.Is(x_x0));
956 VIXL_CHECK(x_x0.Is(r_x0));
957 VIXL_CHECK(r_w0.Is(w_w0));
958 VIXL_CHECK(w_w0.Is(r_w0));
965 VIXL_CHECK(r_x1.Is(x_x1));
966 VIXL_CHECK(x_x1.Is(r_x1));
967 VIXL_CHECK(r_w1.Is(w_w1));
968 VIXL_CHECK(w_w1.Is(r_w1));
975 VIXL_CHECK(cpu_x2.Is(x_x2));
976 VIXL_CHECK(x_x2.Is(cpu_x2));
977 VIXL_CHECK(cpu_w2.Is(w_w2));
978 VIXL_CHECK(w_w2.Is(cpu_w2));
1132 VIXL_CHECK(temp1.Is(w16));
1133 VIXL_CHECK(temp2.Is(x17));
1139 VIXL_CHECK(temp1.Is(x16));
1140 VIXL_CHECK(temp2.Is(w17));
1150 VIXL_CHECK(temp.Is(h31));
1155 VIXL_CHECK(temp.Is(s31));
1160 VIXL_CHECK(temp.Is(d31));
1165 VIXL_CHECK(temp.Is(q31));
1170 VIXL_CHECK(temp.Is(d31));
1175 VIXL_CHECK(temp.Is(s31));
1187 VIXL_CHECK(temp.Is(z31));