Lines Matching refs:result
104 bool Equal32(uint32_t expected, const RegisterDump*, uint32_t result) {
105 if (result != expected) {
108 result);
111 return expected == result;
132 bool Equal64(uint64_t expected, const RegisterDump*, uint64_t result) {
133 if (result != expected) {
136 result);
139 return expected == result;
150 bool Equal128(vec128_t expected, const RegisterDump*, vec128_t result) {
151 if ((result.h != expected.h) || (result.l != expected.l)) {
157 result.h,
158 result.l);
161 return ((expected.h == result.h) && (expected.l == result.l));
170 vec128_t result = core->GetQRegisterBits(qreg.GetCode());
171 return Equal128(expected, core, result);
187 bool EqualNzcv(uint32_t expected, uint32_t result) {
189 VIXL_ASSERT((result & ~NZCVFlag) == 0);
190 if (result != expected) {
196 FlagN(result),
197 FlagZ(result),
198 FlagC(result),
199 FlagV(result));
211 uint32_t result = core->GetSRegisterBits(sreg.GetCode());
213 if (FloatToRawbits(expected) == result) {
219 result);
226 RawbitsToFloat(result),
227 result);
238 uint64_t result = core->GetDRegisterBits(dreg.GetCode());
240 if (DoubleToRawbits(expected) == result) {
247 DoubleToRawbits(result));
254 RawbitsToDouble(result),
255 result);