Lines Matching refs:expected
104 bool Equal32(uint32_t expected, const RegisterDump*, uint32_t result) {
105 if (result != expected) {
107 expected,
111 return expected == result;
115 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg) {
120 return Equal32(expected, core, core->reg(reg.GetCode()));
125 bool Equal32(uint32_t expected,
128 return Equal32(expected, core, core->GetSRegisterBits(sreg.GetCode()));
132 bool Equal64(uint64_t expected, const RegisterDump*, uint64_t result) {
133 if (result != expected) {
135 expected,
139 return expected == result;
143 bool Equal64(uint64_t expected,
146 return Equal64(expected, core, core->GetDRegisterBits(dreg.GetCode()));
150 bool Equal128(vec128_t expected, const RegisterDump*, vec128_t result) {
151 if ((result.h != expected.h) || (result.l != expected.l)) {
155 expected.h,
156 expected.l,
161 return ((expected.h == result.h) && (expected.l == result.l));
169 vec128_t expected = {expected_l, expected_h};
171 return Equal128(expected, core, result);
187 bool EqualNzcv(uint32_t expected, uint32_t result) {
188 VIXL_ASSERT((expected & ~NZCVFlag) == 0);
190 if (result != expected) {
192 FlagN(expected),
193 FlagZ(expected),
194 FlagC(expected),
195 FlagV(expected),
207 bool EqualFP32(float expected,
213 if (FloatToRawbits(expected) == result) {
216 if (IsNaN(expected) || (expected == 0.0)) {
218 FloatToRawbits(expected),
224 expected,
225 FloatToRawbits(expected),
234 bool EqualFP64(double expected,
240 if (DoubleToRawbits(expected) == result) {
244 if (IsNaN(expected) || (expected == 0.0)) {
246 DoubleToRawbits(expected),
252 expected,
253 DoubleToRawbits(expected),