test-disasm-a32.cc - OpenGrok cross reference for /third_party/vixl/test/aarch32/test-disasm-a32.cc

Lines Matching refs:MUST_FAIL_TEST_T32
251 #define MUST_FAIL_TEST_T32(ASM, EXP)       \
256 #define MUST_FAIL_TEST_T32(ASM, EXP)
261   MUST_FAIL_TEST_T32(ASM, EXP)
290 #define MUST_FAIL_TEST_T32(ASM, EXP)                         \
782   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(pc, r0, Offset)),
788   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(pc, r0, PreIndex)),
792   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(pc, r0, PostIndex)),
798   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(r0, minus, pc, Offset)),
801   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(r0, pc, PreIndex)),
804   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(r0, pc, PostIndex)),
820   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(r0, r1, PreIndex)),
822   MUST_FAIL_TEST_T32(Ldr(r0, MemOperand(r0, r1, PostIndex)),
868   MUST_FAIL_TEST_T32(Str(pc, MemOperand(r0, r0, Offset)),
870   MUST_FAIL_TEST_T32(Str(pc, MemOperand(r0, r0, PreIndex)),
872   MUST_FAIL_TEST_T32(Str(pc, MemOperand(r0, r0, PostIndex)),
877   MUST_FAIL_TEST_T32(Str(r0, MemOperand(pc, r0, Offset)),
883   MUST_FAIL_TEST_T32(Str(r0, MemOperand(pc, r0, PreIndex)),
887   MUST_FAIL_TEST_T32(Str(r0, MemOperand(pc, r0, PostIndex)),
893   MUST_FAIL_TEST_T32(Str(r0, MemOperand(r0, minus, pc, Offset)),
896   MUST_FAIL_TEST_T32(Str(r0, MemOperand(r0, pc, PreIndex)),
899   MUST_FAIL_TEST_T32(Str(r0, MemOperand(r0, pc, PostIndex)),
915   MUST_FAIL_TEST_T32(Str(r0, MemOperand(r0, r1, PreIndex)),
917   MUST_FAIL_TEST_T32(Str(r0, MemOperand(r0, r1, PostIndex)),
1457   MUST_FAIL_TEST_T32(Movs(pc, 0x1), "Unpredictable instruction.\n");
1620   MUST_FAIL_TEST_T32(Teq(r0, Operand(r1, LSL, r2)),
1711   MUST_FAIL_TEST_T32(crc32b(eq, r0, r1, r2), "Unpredictable instruction.\n");
1712   MUST_FAIL_TEST_T32(crc32cb(eq, r0, r1, r2), "Unpredictable instruction.\n");
1713   MUST_FAIL_TEST_T32(crc32ch(eq, r0, r1, r2), "Unpredictable instruction.\n");
1714   MUST_FAIL_TEST_T32(crc32cw(eq, r0, r1, r2), "Unpredictable instruction.\n");
1715   MUST_FAIL_TEST_T32(crc32h(eq, r0, r1, r2), "Unpredictable instruction.\n");
1716   MUST_FAIL_TEST_T32(crc32w(eq, r0, r1, r2), "Unpredictable instruction.\n");
1731   MUST_FAIL_TEST_T32(hvc(eq, 0), "Unpredictable instruction.\n");
2009   MUST_FAIL_TEST_T32(fldmiax(pc, NO_WRITE_BACK, DRegisterList(d0)),
2016   MUST_FAIL_TEST_T32(fstmiax(pc, NO_WRITE_BACK, DRegisterList(d0)),
2023   MUST_FAIL_TEST_T32(vldm(pc, NO_WRITE_BACK, SRegisterList(s0)),
2027   MUST_FAIL_TEST_T32(vldmia(pc, NO_WRITE_BACK, SRegisterList(s0)),
2034   MUST_FAIL_TEST_T32(vldm(pc, NO_WRITE_BACK, DRegisterList(d0)),
2038   MUST_FAIL_TEST_T32(vldmia(pc, NO_WRITE_BACK, DRegisterList(d0)),
2045   MUST_FAIL_TEST_T32(vstm(pc, NO_WRITE_BACK, SRegisterList(s0)),
2049   MUST_FAIL_TEST_T32(vstmia(pc, NO_WRITE_BACK, SRegisterList(s0)),
2056   MUST_FAIL_TEST_T32(vstm(pc, NO_WRITE_BACK, DRegisterList(d0)),
2060   MUST_FAIL_TEST_T32(vstmia(pc, NO_WRITE_BACK, DRegisterList(d0)),
2245   MUST_FAIL_TEST_T32(vstr(s0, MemOperand(pc, 0)),
2248   MUST_FAIL_TEST_T32(vstr(d0, MemOperand(pc, 0)),
2339   MUST_FAIL_TEST_T32(Inst(pc, 0xbadbeef),                     \
2341   MUST_FAIL_TEST_T32(Inst(eq, pc, 0xbadbeef),                 \
2519   MUST_FAIL_TEST_T32(Push(RegisterList(sp)), "Unpredictable instruction.\n");
2520   MUST_FAIL_TEST_T32(Push(sp), "Unpredictable instruction.\n");
2531   MUST_FAIL_TEST_T32(Push(pc), "Unpredictable instruction.\n");
2532   MUST_FAIL_TEST_T32(Push(RegisterList(pc)), "Unpredictable instruction.\n");
2534   MUST_FAIL_TEST_T32(Push(RegisterList(r0, pc)),
2595   MUST_FAIL_TEST_T32(Pop(RegisterList(lr, pc)), "Unpredictable instruction.\n");
2612   MUST_FAIL_TEST_T32(Adc(pc, r0, 1), "Unpredictable instruction.\n");
2613   MUST_FAIL_TEST_T32(Adc(r0, pc, 1), "Unpredictable instruction.\n");
2616   MUST_FAIL_TEST_T32(Adcs(pc, r0, 1), "Unpredictable instruction.\n");
2617   MUST_FAIL_TEST_T32(Adcs(r0, pc, 1), "Unpredictable instruction.\n");
2623   MUST_FAIL_TEST_T32(Adc(pc, r0, r1), "Unpredictable instruction.\n");
2624   MUST_FAIL_TEST_T32(Adc(r0, pc, r1), "Unpredictable instruction.\n");
2625   MUST_FAIL_TEST_T32(Adc(r0, r1, pc), "Unpredictable instruction.\n");
2629   MUST_FAIL_TEST_T32(Adcs(pc, r0, r1), "Unpredictable instruction.\n");
2630   MUST_FAIL_TEST_T32(Adcs(r0, pc, r1), "Unpredictable instruction.\n");
2631   MUST_FAIL_TEST_T32(Adcs(r0, r1, pc), "Unpredictable instruction.\n");
2655   MUST_FAIL_TEST_T32(Add(pc, pc, 1), "Unpredictable instruction.\n");
2659   MUST_FAIL_TEST_T32(Add(pc, r0, 1), "Unpredictable instruction.\n");
2660   MUST_FAIL_TEST_T32(Add(pc, r0, 0x123), "Unpredictable instruction.\n");
2664   MUST_FAIL_TEST_T32(Adds(r0, pc, 1), "Unpredictable instruction.\n");
2665   MUST_FAIL_TEST_T32(Adds(r0, pc, 0x123), "Ill-formed 'adds' instruction.\n");
2673   MUST_FAIL_TEST_T32(Add(pc, pc, pc), "Unpredictable instruction.\n");
2674   MUST_FAIL_TEST_T32(Add(pc, r0, r1), "Unpredictable instruction.\n");
2675   MUST_FAIL_TEST_T32(Add(r0, pc, r1), "Unpredictable instruction.\n");
2676   MUST_FAIL_TEST_T32(Add(r0, r1, pc), "Unpredictable instruction.\n");
2680   MUST_FAIL_TEST_T32(Adds(r0, pc, r1), "Unpredictable instruction.\n");
2681   MUST_FAIL_TEST_T32(Adds(r0, r1, pc), "Unpredictable instruction.\n");
2693   MUST_FAIL_TEST_T32(Add(pc, sp, 1), "Unpredictable instruction.\n");
2705   MUST_FAIL_TEST_T32(Add(pc, sp, 1), "Unpredictable instruction.\n");
2707   MUST_FAIL_TEST_T32(Adds(pc, sp, 1), "Ill-formed 'adds' instruction.\n");
2711   MUST_FAIL_TEST_T32(Add(pc, sp, r0), "Unpredictable instruction.\n");
2713   MUST_FAIL_TEST_T32(Add(r0, sp, pc), "Unpredictable instruction.\n");
2717   MUST_FAIL_TEST_T32(Adds(pc, sp, r0), "Ill-formed 'adds' instruction.\n");
2719   MUST_FAIL_TEST_T32(Adds(r0, sp, pc), "Unpredictable instruction.\n");
2721   MUST_FAIL_TEST_T32(Adds(pc, sp, pc), "Ill-formed 'adds' instruction.\n");
2723   MUST_FAIL_TEST_T32(Adds(sp, sp, pc), "Unpredictable instruction.\n");
2731     MUST_FAIL_TEST_T32(Adr(pc, &literal), "Unpredictable instruction.\n");
2740   MUST_FAIL_TEST_T32(Mov(pc, 1), "Unpredictable instruction.\n");
2741   MUST_FAIL_TEST_T32(Mov(pc, 0xfff), "Unpredictable instruction.\n");
2743   MUST_FAIL_TEST_T32(Mov(pc, 0xf000), "Unpredictable instruction.\n");
2745   MUST_FAIL_TEST_T32(Movs(pc, 1), "Unpredictable instruction.\n");
2748   MUST_FAIL_TEST_T32(Movs(pc, 0xf000), "Unpredictable instruction.\n");
2755   MUST_FAIL_TEST_T32(Movs(r0, pc), "Unpredictable instruction.\n");
2882   MUST_FAIL_TEST_T32(Add(r0, pc, 4096), "Unpredictable instruction.\n");
2884   MUST_FAIL_TEST_T32(Add(r0, pc, -4096), "Unpredictable instruction.\n");
2886   MUST_FAIL_TEST_T32(Add(r0, pc, 0xffff), "Ill-formed 'add' instruction.\n");
2887   MUST_FAIL_TEST_T32(Add(r0, pc, 0x10002), "Ill-formed 'add' instruction.\n");
2888   MUST_FAIL_TEST_T32(Add(r0, pc, 0x12345678),
2890   MUST_FAIL_TEST_T32(Add(r0, pc, 0x7fffffff),
2908   MUST_FAIL_TEST_T32(Sub(r0, pc, 4096), "Unpredictable instruction.\n");
2910   MUST_FAIL_TEST_T32(Sub(r0, pc, -0xffff), "Ill-formed 'add' instruction.\n");
2911   MUST_FAIL_TEST_T32(Sub(r0, pc, -0x10002), "Ill-formed 'add' instruction.\n");
2912   MUST_FAIL_TEST_T32(Sub(r0, pc, -0x12345678),
2914   MUST_FAIL_TEST_T32(Sub(r0, pc, -0x7fffffff),
3682   MUST_FAIL_TEST_T32(Sub(eq, pc, pc, 0), "Unpredictable instruction.\n");