test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc - OpenGrok cross reference for /third_party/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc

Lines Matching refs:ls
132      {{ls, r7, r7, r2}, true, ls, "ls r7 r7 r2", "ls_r7_r7_r2"},
139      {{ls, r5, r5, r4}, true, ls, "ls r5 r5 r4", "ls_r5_r5_r4"},
145      {{ls, r5, r5, r0}, true, ls, "ls r5 r5 r0", "ls_r5_r5_r0"},
146      {{ls, r2, r2, r5}, true, ls, "ls r2 r2 r5", "ls_r2_r2_r5"},
147      {{ls, r0, r0, r3}, true, ls, "ls r0 r0 r3", "ls_r0_r0_r3"},
150      {{ls, r5, r5, r3}, true, ls, "ls r5 r5 r3", "ls_r5_r5_r3"},
156      {{ls, r0, r0, r1}, true, ls, "ls r0 r0 r1", "ls_r0_r0_r1"},
166      {{ls, r6, r6, r1}, true, ls, "ls r6 r6 r1", "ls_r6_r6_r1"},
168      {{ls, r6, r6, r7}, true, ls, "ls r6 r6 r7", "ls_r6_r6_r7"},
177      {{ls, r7, r7, r6}, true, ls, "ls r7 r7 r6", "ls_r7_r7_r6"},
210      {{ls, r0, r0, r0}, true, ls, "ls r0 r0 r0", "ls_r0_r0_r0"},
221      {{ls, r7, r7, r1}, true, ls, "ls r7 r7 r1", "ls_r7_r7_r1"},
235      {{ls, r7, r7, r3}, true, ls, "ls r7 r7 r3", "ls_r7_r7_r3"},
243      {{ls, r3, r3, r2}, true, ls, "ls r3 r3 r2", "ls_r3_r3_r2"},
248      {{ls, r2, r2, r6}, true, ls, "ls r2 r2 r6", "ls_r2_r2_r6"},
254      {{ls, r7, r7, r5}, true, ls, "ls r7 r7 r5", "ls_r7_r7_r5"},
255      {{ls, r1, r1, r5}, true, ls, "ls r1 r1 r5", "ls_r1_r1_r5"},
260      {{ls, r7, r7, r4}, true, ls, "ls r7 r7 r4", "ls_r7_r7_r4"},
286      {{ls, r6, r6, r6}, true, ls, "ls r6 r6 r6", "ls_r6_r6_r6"},
300      {{ls, r3, r3, r3}, true, ls, "ls r3 r3 r3", "ls_r3_r3_r3"},
327      {{ls, r1, r1, r0}, true, ls, "ls r1 r1 r0", "ls_r1_r1_r0"},
353      {{ls, r4, r4, r2}, true, ls, "ls r4 r4 r2", "ls_r4_r4_r2"},
361      {{ls, r1, r1, r7}, true, ls, "ls r1 r1 r7", "ls_r1_r1_r7"},
363      {{ls, r5, r5, r2}, true, ls, "ls r5 r5 r2", "ls_r5_r5_r2"},
364      {{ls, r6, r6, r2}, true, ls, "ls r6 r6 r2", "ls_r6_r6_r2"},
401      {{ls, r5, r5, r6}, true, ls, "ls r5 r5 r6", "ls_r5_r5_r6"},
405      {{ls, r6, r6, r3}, true, ls, "ls r6 r6 r3", "ls_r6_r6_r3"},
406      {{ls, r6, r6, r0}, true, ls, "ls r6 r6 r0", "ls_r6_r6_r0"},
421      {{ls, r3, r3, r4}, true, ls, "ls r3 r3 r4", "ls_r3_r3_r4"},
456      {{ls, r3, r3, r1}, true, ls, "ls r3 r3 r1", "ls_r3_r3_r1"},
483      {{ls, r2, r2, r2}, true, ls, "ls r2 r2 r2", "ls_r2_r2_r2"},
485      {{ls, r2, r2, r7}, true, ls, "ls r2 r2 r7", "ls_r2_r2_r7"},
513      {{ls, r4, r4, r4}, true, ls, "ls r4 r4 r4", "ls_r4_r4_r4"},
518      {{ls, r0, r0, r4}, true, ls, "ls r0 r0 r4", "ls_r0_r0_r4"},
561      {{ls, r0, r0, r2}, true, ls, "ls r0 r0 r2", "ls_r0_r0_r2"},
593      {{ls, r5, r5, r1}, true, ls, "ls r5 r5 r1", "ls_r5_r5_r1"},