test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc - OpenGrok cross reference for /third_party/vixl/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc

Lines Matching refs:ls
99      {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
102      {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"},
105      {{ls, r3, r4, r0}, true, ls, "ls r3 r4 r0", "ls_r3_r4_r0"},
115      {{ls, r3, r3, r1}, true, ls, "ls r3 r3 r1", "ls_r3_r3_r1"},
130      {{ls, r3, r1, r3}, true, ls, "ls r3 r1 r3", "ls_r3_r1_r3"},
144      {{ls, r2, r7, r5}, true, ls, "ls r2 r7 r5", "ls_r2_r7_r5"},
146      {{ls, r1, r6, r2}, true, ls, "ls r1 r6 r2", "ls_r1_r6_r2"},
151      {{ls, r1, r6, r7}, true, ls, "ls r1 r6 r7", "ls_r1_r6_r7"},
190      {{ls, r7, r5, r4}, true, ls, "ls r7 r5 r4", "ls_r7_r5_r4"},
202      {{ls, r6, r1, r6}, true, ls, "ls r6 r1 r6", "ls_r6_r1_r6"},
212      {{ls, r5, r7, r6}, true, ls, "ls r5 r7 r6", "ls_r5_r7_r6"},
215      {{ls, r1, r4, r3}, true, ls, "ls r1 r4 r3", "ls_r1_r4_r3"},
223      {{ls, r3, r7, r3}, true, ls, "ls r3 r7 r3", "ls_r3_r7_r3"},
228      {{ls, r0, r0, r1}, true, ls, "ls r0 r0 r1", "ls_r0_r0_r1"},
243      {{ls, r3, r3, r7}, true, ls, "ls r3 r3 r7", "ls_r3_r3_r7"},
251      {{ls, r4, r2, r0}, true, ls, "ls r4 r2 r0", "ls_r4_r2_r0"},
253      {{ls, r6, r1, r3}, true, ls, "ls r6 r1 r3", "ls_r6_r1_r3"},
277      {{ls, r1, r7, r2}, true, ls, "ls r1 r7 r2", "ls_r1_r7_r2"},
281      {{ls, r6, r3, r1}, true, ls, "ls r6 r3 r1", "ls_r6_r3_r1"},
288      {{ls, r5, r3, r6}, true, ls, "ls r5 r3 r6", "ls_r5_r3_r6"},
290      {{ls, r4, r6, r5}, true, ls, "ls r4 r6 r5", "ls_r4_r6_r5"},
318      {{ls, r2, r1, r5}, true, ls, "ls r2 r1 r5", "ls_r2_r1_r5"},
326      {{ls, r3, r0, r7}, true, ls, "ls r3 r0 r7", "ls_r3_r0_r7"},
339      {{ls, r0, r5, r7}, true, ls, "ls r0 r5 r7", "ls_r0_r5_r7"},
404      {{ls, r1, r3, r7}, true, ls, "ls r1 r3 r7", "ls_r1_r3_r7"},
425      {{ls, r2, r4, r6}, true, ls, "ls r2 r4 r6", "ls_r2_r4_r6"},
450      {{ls, r4, r4, r6}, true, ls, "ls r4 r4 r6", "ls_r4_r4_r6"},
456      {{ls, r0, r3, r7}, true, ls, "ls r0 r3 r7", "ls_r0_r3_r7"},
490      {{ls, r0, r4, r6}, true, ls, "ls r0 r4 r6", "ls_r0_r4_r6"},
497      {{ls, r5, r5, r6}, true, ls, "ls r5 r5 r6", "ls_r5_r5_r6"},
501      {{ls, r0, r4, r3}, true, ls, "ls r0 r4 r3", "ls_r0_r4_r3"},
546      {{ls, r4, r5, r3}, true, ls, "ls r4 r5 r3", "ls_r4_r5_r3"},
568      {{ls, r1, r3, r6}, true, ls, "ls r1 r3 r6", "ls_r1_r3_r6"},
579      {{ls, r2, r5, r5}, true, ls, "ls r2 r5 r5", "ls_r2_r5_r5"},
586      {{ls, r1, r7, r4}, true, ls, "ls r1 r7 r4", "ls_r1_r7_r4"},
594      {{ls, r3, r1, r5}, true, ls, "ls r3 r1 r5", "ls_r3_r1_r5"},