Lines Matching refs:src1
3414 const LogicVRegister& src1,
3419 const LogicVRegister& src1,
3424 const LogicVRegister& src1,
3428 const LogicVRegister& src1,
3430 // Add `value` to each lane of `src1`, treating `value` as unsigned for the
3434 const LogicVRegister& src1,
3438 const LogicVRegister& src1,
3457 // dst = srca + src1 * src2
3461 const LogicVRegister& src1,
3463 // dst = srca - src1 * src2
3467 const LogicVRegister& src1,
3471 const LogicVRegister& src1,
3475 const LogicVRegister& src1,
3480 const LogicVRegister& src1,
3485 const LogicVRegister& src1,
3490 const LogicVRegister& src1,
3494 const LogicVRegister& src1,
3498 const LogicVRegister& src1,
3503 const LogicVRegister& src1,
3508 const LogicVRegister& src1,
3513 const LogicVRegister& src1,
3518 const LogicVRegister& src1,
3523 const LogicVRegister& src1,
3528 const LogicVRegister& src1,
3533 const LogicVRegister& src1,
3538 const LogicVRegister& src1,
3543 const LogicVRegister& src1,
3548 const LogicVRegister& src1,
3552 const LogicVRegister& src1,
3556 const LogicVRegister& src1,
3561 const LogicVRegister& src1,
3566 const LogicVRegister& src1,
3571 const LogicVRegister& src1,
3576 const LogicVRegister& src1,
3581 const LogicVRegister& src1,
3586 const LogicVRegister& src1,
3591 const LogicVRegister& src1,
3593 // Subtract `value` from each lane of `src1`, treating `value` as unsigned for
3597 const LogicVRegister& src1,
3601 const LogicVRegister& src1,
3605 const LogicVRegister& src1,
3609 const LogicVRegister& src1,
3613 const LogicVRegister& src1,
3617 const LogicVRegister& src1,
3625 const LogicVRegister& src1,
3629 const LogicVRegister& src1,
3634 const LogicVRegister& src1,
3693 const LogicVRegister& src1,
3703 const LogicVRegister& src1,
3708 const LogicVRegister& src1,
3714 const LogicVRegister& src1,
3721 const LogicVRegister& src1,
3727 const LogicVRegister& src1,
3742 const LogicVRegister& src1,
3749 const LogicVRegister& src1,
3755 const LogicVRegister& src1,
3761 const LogicVRegister& src1,
3766 const LogicVRegister& src1,
3771 const LogicVRegister& src1,
3833 const LogicVRegister& src1,
3838 const LogicVRegister& src1,
3843 const LogicVRegister& src1,
3847 const LogicVRegister& src1,
3869 const LogicVRegister& src1,
3874 const LogicVRegister& src1,
3878 const LogicPRegister& src1,
3882 const LogicVRegister& src1,
3887 const LogicVRegister& src1,
3891 const LogicVRegister& src1,
3895 const LogicVRegister& src1,
3900 const LogicVRegister& src1,
3904 const LogicVRegister& src1,
4005 const LogicVRegister& src1,
4009 const LogicVRegister& src1,
4013 const LogicVRegister& src1,
4017 const LogicVRegister& src1,
4021 const LogicVRegister& src1,
4025 const LogicVRegister& src1,
4029 const LogicVRegister& src1,
4033 const LogicVRegister& src1,
4037 const LogicVRegister& src1,
4041 const LogicVRegister& src1,
4045 const LogicVRegister& src1,
4049 const LogicVRegister& src1,
4053 const LogicVRegister& src1,
4057 const LogicVRegister& src1,
4061 const LogicVRegister& src1,
4065 const LogicVRegister& src1,
4069 const LogicVRegister& src1,
4074 const LogicVRegister& src1,
4078 const LogicVRegister& src1,
4082 const LogicVRegister& src1,
4087 const LogicVRegister& src1,
4091 const LogicVRegister& src1,
4106 const LogicVRegister& src1,
4110 const LogicVRegister& src1,
4114 const LogicVRegister& src1,
4118 const LogicVRegister& src1,
4122 const LogicVRegister& src1,
4126 const LogicVRegister& src1,
4214 const LogicVRegister& src1,
4218 const LogicVRegister& src1,
4257 const LogicVRegister& src1,
4262 const LogicVRegister& src1,
4266 const LogicVRegister& src1,
4334 const LogicVRegister& src1,
4339 const LogicVRegister& src1,
4345 const LogicVRegister& src1,
4349 const LogicVRegister& src1,
4353 const LogicVRegister& src1,
4358 const LogicVRegister& src1,
4364 const LogicVRegister& src1,
4370 const LogicVRegister& src1,
4376 const LogicVRegister& src1,
4382 const LogicVRegister& src1,
4388 const LogicVRegister& src1,
4393 const LogicVRegister& src1,
4398 const LogicVRegister& src1,
4402 const LogicVRegister& src1,
4409 const LogicVRegister& src1,
4413 const LogicVRegister& src1,
4447 const LogicVRegister& src1, \
4466 const LogicVRegister& src1, \
4487 const LogicVRegister& src1, \
4491 const LogicVRegister& src1, \
4506 const LogicVRegister& src1, \
4523 const LogicVRegister& src1,
4527 const LogicVRegister& src1,
4532 const LogicVRegister& src1,
4536 const LogicVRegister& src1,
4542 const LogicVRegister& src1,
4547 const LogicVRegister& src1,
4553 const LogicVRegister& src1,
4558 const LogicVRegister& src1,
4562 const LogicVRegister& src1,
4567 const LogicVRegister& src1,
4571 const LogicVRegister& src1,
4575 const LogicVRegister& src1,
4579 const LogicVRegister& src1,
4585 const LogicVRegister& src1,
4590 const LogicVRegister& src1,
4595 const LogicVRegister& src1,
4619 const LogicVRegister& src1,
4623 const LogicVRegister& src1,
4627 const LogicVRegister& src1,
4639 const LogicVRegister& src1,
4643 const LogicVRegister& src1,
4654 const LogicVRegister& src1,
4740 const LogicVRegister& src1,
4962 const LogicVRegister& src1,
5018 const LogicVRegister& src1,
5039 const LogicVRegister& src1,
5046 const LogicVRegister& src1,